Travelled to:1 × The Netherlands
2 × France
2 × USA
Collaborated with:S.Derrien D.Menard C.Huriaux A.Courtay V.D.Tovinakere M.A.Pasha A.Floch T.Yuki A.E.Moussawi A.Morvan K.Martin M.Naullet M.Alle L.L'Hours N.Simon F.Charot C.Wolinski
Talks about:design (3) flow (3) power (2) time (2) architectur (1) semiempir (1) framework (1) algorithm (1) prototyp (1) configur (1)
Person: Olivier Sentieys
DBLP: Sentieys:Olivier
Contributed to:
2015
2013
201220102002Wrote 5 papers:
- DATE-2015-HuriauxCS #design #runtime
- Design flow and run-time management for compressed FPGA configurations (CH, AC, OS), pp. 1551–1554.
- SCAM-2013-FlochYMMMNALSDCWS #design #framework #hardware #named #prototype
- GeCoS: A framework for prototyping custom hardware design flows (AF, TY, AEM, AM, KM, MN, MA, LL, NS, SD, FC, CW, OS), pp. 100–105.
- DAC-2012-TovinakereSD #clustering #estimation #logic
- A semiempirical model for wakeup time estimation in power-gated logic clusters (VDT, OS, SD), pp. 48–55.
- DAC-2010-PashaDS #architecture #generative #power management
- A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking (MAP, SD, OS), pp. 693–698.
- DATE-2002-MenardS #algorithm #automation #evaluation #fixpoint
- Automatic Evaluation of the Accuracy of Fixed-Point Algorithms (DM, OS), pp. 529–535.