1 × China
1 × Germany
2 × France
3 × USA
C.J.Xue Y.He M.Zhao J.Hu Y.Liu K.Qiu L.Jiang Y.Zhang M.Xie Y.Chen N.Jiang C.Xu J.Li L.Shi Y.Chen Y.Xu
volatil (5) system (3) compil (3) cach (3) pcm (3) perform (2) direct (2) assist (2) write (2) stack (2)
Person: Qing'an Li
Wrote 7 papers:
- DAC-2015-LiZHLHX #automation #compilation #performance #stack
- Compiler directed automatic stack trimming for efficient non-volatile processors (QL, MZ, JH, YL, YH, CJX), p. 6.
- DATE-2015-ZhaoLXLHX #cyber-physical #energy #reduction
- Software assisted non-volatile register reduction for energy harvesting based cyber-physical system (MZ, QL, MX, YL, JH, CJX), pp. 567–572.
- DAC-2014-QiuLX #performance #power management
- Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM (KQ, QL, CJX), p. 6.
- DATE-2014-LiHCXJX #embedded #memory management #stack
- A wear-leveling-aware dynamic stack for PCM memory in embedded systems (QL, YH, YC, CJX, NJ, CX), pp. 1–4.
- DATE-2013-LiSLXCX #adaptation
- Cache coherence enabled adaptive refresh for volatile STT-RAM (JL, LS, QL, CJX, YC, YX), pp. 1247–1250.
- LCTES-2013-LiJZHX #compilation #performance #power management
- Compiler directed write-mode selection for high performance low power volatile PCM (QL, LJ, YZ, YH, CJX), pp. 101–110.
- LCTES-2012-LiZXH #embedded #hybrid
- Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache (QL, MZ, CJX, YH), pp. 109–118.