Travelled to:1 × USA
2 × France
2 × Germany
Collaborated with:F.Fummi N.Bombieri G.Pravadelli V.Bertacco D.Chatterjee M.Lora F.Stefanni D.Trachanis J.Vanhese M.Becker G.B.Defo W.Müller A.M.Kaushik H.D.Patel V.Guarnieri M.Petricca A.Sassone E.Macii M.Poncino
Talks about:system (3) acceler (2) verif (2) simul (2) embed (2) architectur (1) methodolog (1) testbench (1) heterogen (1) construct (1)
Person: Sara Vinco
DBLP: Vinco:Sara
Contributed to:
20142013
201220122009Wrote 6 papers:
- DATE-2014-FummiLSTVV #design #effectiveness #simulation
- Moving from co-simulation to simulation for effective smart systems design (FF, ML, FS, DT, JV, SV), pp. 1–4.
- DATE-2014-GuarnieriPSVBFMP #embedded #monitoring #verification
- A cross-level verification methodology for digital IPs augmented with embedded timing monitors (VG, MP, AS, SV, NB, FF, EM, MP), pp. 1–6.
- DATE-2013-BertaccoCBFVKP #on the #using
- On the use of GP-GPUs for accelerating compute-intensive EDA applications (VB, DC, NB, FF, SV, AMK, HDP), pp. 1357–1366.
- DAC-2012-VincoCBF #architecture #gpu #named
- SAGA: SystemC acceleration on GPU architectures (SV, DC, VB, FF), pp. 115–120.
- DATE-2012-BeckerDFMPV #embedded #evolution #modelling #named #scalability #verification
- MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution (MB, GBD, FF, WM, GP, SV), pp. 296–299.
- DATE-2009-BombieriFPV #generative
- Correct-by-construction generation of device drivers based on RTL testbenches (NB, FF, GP, SV), pp. 1500–1505.