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Travelled to:
2 × Germany
3 × France
4 × USA
Collaborated with:
P.Schaumont R.Cmar I.Bolsens M.Engels D.Verkest R.Lauwereins L.Rijnders B.Mei V.Nollet J.Mignolet R.Pasko T.Marescaux H.D.Man P.Coene E.Berrebi P.Kission S.D.Troch J.Herluison J.Fréhel A.A.Jerraya
Talks about:
design (5) high (4) architectur (3) reconfigur (3) system (3) level (3) methodolog (2) synthesi (2) parallel (2) environ (2)

Person: Serge Vernalde

DBLP DBLP: Vernalde:Serge

Contributed to:

DAC 20042004
DATE v2 20042004
DATE 20032003
DATE 20022002
DAC 19991999
DATE 19991999
DAC 19981998
ED&TC 19971997
DAC 19961996

Wrote 12 papers:

DAC-2004-NolletMVMV #network
Operating-system controlled network on chip (VN, TM, DV, JYM, SV), pp. 256–259.
DATE-v2-2004-MeiVVL #architecture #case study #configuration management #design #matrix
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study (BM, SV, DV, RL), pp. 1224–1229.
DATE-2003-MeiVVML #architecture #configuration management #parallel #scheduling #using
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling (BM, SV, DV, HDM, RL), pp. 10296–10301.
DATE-2003-MignoletNCVVL #configuration management #design #framework
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip (JYM, VN, PC, DV, SV, RL), pp. 10986–10993.
DATE-2002-PaskoVS #c++ #design
Techniques to Evolve a C++ Based System Design Language (RP, SV, PS), pp. 302–309.
DAC-1999-SchaumontCVE #automation
A 10 Mbit/s Upstream Cable Modem with Automatic equalization (PS, RC, SV, ME), pp. 337–340.
DAC-1999-SchaumontCVEB #behaviour #hardware #reuse
Hardware Reuse at the Behavioral Level (PS, RC, SV, ME, IB), pp. 784–789.
DATE-1999-CmarRSVB #design #fixpoint #refinement
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement (RC, LR, PS, SV, IB), p. 271–?.
DAC-1998-SchaumontVREB #design #programming
A Programming Environment for the Design of Complex High Speed ASICs (PS, SV, LR, ME, IB), pp. 315–320.
EDTC-1997-CmarV #architecture #parallel #scalability
Highly scalable parallel parametrizable architecture of the motion estimator (RC, SV), pp. 208–212.
EDTC-1997-SchaumontVREB #multi #synthesis
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications (PS, SV, LR, ME, IB), pp. 542–546.
DAC-1996-BerrebiKVTHFJB #control flow #data flow #synthesis
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis (EB, PK, SV, SDT, JCH, JF, AAJ, IB), pp. 573–578.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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