BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × Germany
3 × USA
Collaborated with:
W.M.v.Cleemput J.Shin H.Kim Y.Hur S.A.Szygenda E.S.Fehr G.E.Ott
Talks about:
interconnect (1) processor (1) placement (1) synthesi (1) parallel (1) descript (1) boundari (1) multipl (1) automat (1) system (1)

Person: Sungho Kang

DBLP DBLP: Kang:Sungho

Contributed to:

DATE 19991999
HPCA 19951995
DAC 19831983
DAC 19811981

Wrote 4 papers:

DATE-1999-ShinKK #bound #multi #testing
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks (JS, HK, SK), p. 473–?.
HPCA-1995-HurSFOK #array #design #fault #logic #parallel #simulation
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation (YH, SAS, ESF, GEO, SK), pp. 340–347.
DAC-1983-Kang #linear
Linear ordering and application to placement (SK), pp. 457–464.
DAC-1981-KangC #automation #synthesis
Automatic PLA synthesis from a DDL-P description (SK, WMvC), pp. 391–397.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.