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Travelled to:
2 × France
2 × Germany
2 × USA
Collaborated with:
A.Orailoglu R.Karri Y.Su I.Bayraktaroglu
Talks about:
toler (3) logic (3) base (3) nanoelectron (2) crossbar (2) compress (2) fault (2) test (2) architectur (1) nanosystem (1)

Person: Wenjing Rao

DBLP DBLP: Rao:Wenjing

Contributed to:

DATE 20132013
DATE 20082008
DATE 20072007
DAC 20062006
DAC 20032003
DATE 20032003

Wrote 6 papers:

DATE-2013-SuR #logic
Defect-tolerant logic hardening for crossbar-based nanosystems (YS, WR), pp. 1801–1806.
DATE-2008-RaoO #fault tolerance #parallel #towards
Towards fault tolerant parallel prefix adders in nanoelectronic systems (WR, AO), pp. 360–365.
DATE-2007-RaoOK #fault tolerance #interactive #logic
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs (WR, AO, RK), pp. 865–869.
DAC-2006-RaoOK #architecture #logic
Topology aware mapping of logic functions onto nanowire-based crossbar architectures (WR, AO, RK), pp. 723–726.
Test application time and volume compression through seed overlapping (WR, IB, AO), pp. 732–737.
DATE-2003-RaoO #design
Virtual Compression through Test Vector Stitching for Scan Based Designs (WR, AO), pp. 10104–10109.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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