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Travelled to:
1 × France
2 × Germany
Collaborated with:
A.G.Veneris N.Nicolici P.J.Thadikaran S.Venkataraman Z.Poulos J.Anderson B.Le S.Sinha R.K.Brayton D.E.Smith
Talks about:
debug (3) model (2) autom (2) reconfigur (1) sequenti (1) function (1) approxim (1) silicon (1) product (1) perform (1)

Person: Yu-Shen Yang

DBLP DBLP: Yang:Yu=Shen

Contributed to:

DATE 20122012
DATE 20092009
DATE 20052005

Wrote 4 papers:

DATE-2012-PoulosYAVL #debugging #functional
Leveraging reconfigurability to raise productivity in FPGA functional debug (ZP, YSY, JA, AGV, BL), pp. 292–295.
DATE-2009-YangNV #automation #data analysis #debugging
Automated data analysis solutions to silicon debug (YSY, NN, AGV), pp. 982–987.
DATE-2009-YangSVBS #approximate #logic
Sequential logic rectifications with approximate SPFDs (YSY, SS, AGV, RKB, DES), pp. 1698–1703.
DATE-2005-YangVTV #automation #debugging #design #fault #modelling #power management
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs (YSY, AGV, PJT, SV), pp. 996–1001.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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