BibSLEIGH — Nicola

Travelled to:

4 × Germany
4 × USA
6 × France

Collaborated with:

B.M.Al-Hashimi A.B.Kinsman H.F.Ko Q.Xu P.T.Gonciari P.Taatizadeh P.Kinsman K.Elizeh J.Thong E.Anis S.Mitra S.A.Seshia Y.Yang A.G.Veneris K.Chakrabarty D.Gizopoulos K.Roy P.Girard X.Wen

Talks about:

test (8) silicon (6) design (5) valid (5) data (5) compress (4) system (4) power (4) autom (4) post (4)

Person: Nicola Nicolici

DBLP: Nicolici:Nicola

Contributed to:

2015

2013

2011

2010

2009

2008

2007

2005

2004

2003

2002

2001

2000

1999

Wrote 21 papers:

DATE-2015-TaatizadehN #automation #design #detection #embedded #validation: A methodology for automated design of embedded bit-flips detectors in post-silicon validation (PT, NN), pp. 73–78.
DAC-2013-KinsmanKN #generative #sequence #validation: Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation (ABK, HFK, NN), p. 6.
DAC-2011-KinsmanN #configuration management #on the fly: Dynamic binary translation to a reconfigurable target for on-the-fly acceleration (PK, NN), pp. 286–287.
DAC-2010-ElizehN #embedded #memory management: Embedded memory binding in FPGAs (KE, NN), pp. 457–462.
DAC-2010-KinsmanN #algorithm #design #hardware #robust: Robust design methods for hardware accelerators for iterative algorithms in scientific computing (ABK, NN), pp. 254–257.
DAC-2010-MitraSN #challenge #validation: Post-silicon validation opportunities, challenges and recent advances (SM, SAS, NN), pp. 12–17.
DAC-2010-ThongN #algorithm #constant #multi #novel: A novel optimal single constant multiplication algorithm (JT, NN), pp. 613–616.
DATE-2009-KinsmanN #finite #modulo theories #precise #using: Finite Precision bit-width allocation using SAT-Modulo Theory (ABK, NN), pp. 1106–1111.
DATE-2009-YangNV #automation #data analysis #debugging: Automated data analysis solutions to silicon debug (YSY, NN, AGV), pp. 982–987.
DATE-2008-GizopoulosRGNW #power management #testing: Power-Aware Testing and Test Strategies for Low Power Devices (DG, KR, PG, NN, XW).
DATE-2008-KoN #automation #identification #validation: Automated Trace Signals Identification and State Restoration for Improving Observability in Post-Silicon Validation (HFK, NN), pp. 1298–1303.
DATE-2008-KoN08a #automation #generative #on the #validation: On Automated Trigger Event Generation in Post-Silicon Validation (HFK, NN), pp. 256–259.
DATE-2007-AnisN #architecture #debugging #interactive #low cost #using: Interactive presentation: Low cost debug architecture using lossy compression for silicon debug (EA, NN), pp. 225–230.
DAC-2005-XuNC #constraints #design #embedded #multi #optimisation: Multi-frequency wrapper design and optimization for embedded cores under average power constraints (QX, NN, KC), pp. 123–128.
DATE-v1-2004-XuN #design #multi #testing: Wrapper Design for Testing IP Cores with Multiple Clock Domains (QX, NN), pp. 416–421.
DATE-2003-GonciariAN #perspective #testing: Test Data Compression: The System Integrator’s Perspective (PTG, BMAH, NN), pp. 10726–10731.
DATE-2003-XuN #fault #testing: Delay Fault Testing of Core-Based Systems-on-a-Chi (QX, NN), pp. 10744–10752.
DATE-2002-GonciariAN #testing: Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression (PTG, BMAH, NN), pp. 604–611.
DATE-2001-NicoliciA #3d #design #testing #trade-off: Testability trade-offs for BIST RTL data paths: the case for three dimensional design space (NN, BMAH), p. 802.
DATE-2000-NicoliciA #clustering #multi #power management: Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits (NN, BMAH), pp. 715–722.
DATE-1999-NicoliciA #hardware #performance: Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths (NN, BMAH), p. 289–?.