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Travelled to:
1 × France
1 × Germany
3 × USA
Collaborated with:
W.K.Fuchs J.H.Patel Y.Yang A.G.Veneris P.J.Thadikaran I.Pomeranz S.M.Reddy B.Seshadri D.Xiang I.Hartanto E.M.Rudnick S.Chakravarty R.Puri S.Griffith A.Oberai R.Madge G.Yeric W.Ng Y.Zorian
Talks about:
circuit (3) fault (3) design (2) model (2) characterist (1) manufactur (1) simplifi (1) sequenti (1) diagnost (1) diagnosi (1)

Person: Srikanth Venkataraman

DBLP DBLP: Venkataraman:Srikanth

Contributed to:

DAC 20072007
DATE 20052005
DATE v1 20042004
DAC 19961996
DAC 19951995

Wrote 5 papers:

Making Manufacturing Work For You (SV, RP, SG, AO, RM, GY, WN, YZ), pp. 107–108.
DATE-2005-YangVTV #automation #debugging #design #fault #modelling #power management
Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs (YSY, AGV, PJT, SV), pp. 996–1001.
DATE-v1-2004-PomeranzVRS #detection #fault
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis (IP, SV, SMR, BS), pp. 68–75.
DAC-1996-XiangVFP #design
Partial Scan Design Based on Circuit State Information (DX, SV, WKF, JHP), pp. 807–812.
DAC-1995-VenkataramanHFRCP #agile #fault #simulation #using
Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists (SV, IH, WKF, EMR, SC, JHP), pp. 133–138.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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