Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
DAC, 1995.
@inproceedings{DAC-1995-MenezesPP,
author = "Noel Menezes and Satyamurthy Pullela and Lawrence T. Pileggi",
booktitle = "{Proceedings of the 32nd Design Automation Conference}",
doi = "10.1145/217474.217612",
isbn = "0-89791-725-1",
pages = "690--695",
publisher = "{ACM Press}",
title = "{Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization}",
year = 1995,
}