BibSLEIGH — Proceedings of the 32nd Design Automation Conference

Bryan Preas
Proceedings of the 32nd Design Automation Conference
DAC, 1995.

SYS

@proceedings{DAC-1995,
	acmid         = "217474",
	address       = "San Francisco, California, USA",
	editor        = "Bryan Preas",
	isbn          = "0-89791-725-1",
	publisher     = "{ACM Press}",
	title         = "{Proceedings of the 32nd Design Automation Conference}",
	year          = 1995,
}

Contents (122 items)

DAC-1995-TremblayMIK #analysis #architecture #flexibility #performance #trade-off: A Fast and Flexible Performance Simulator for Micro-Architecture Trade-off Analysis on UltraSPARC-I (MT, GM, AI, LK), pp. 2–6.
DAC-1995-YangGMJL #design: System Design Methodology of UltraSPARC-I (LY, DG, JM, RJ, PL), pp. 7–12.
DAC-1995-GateleyBCCDDEFGGJKKMNNOPSSWW: UltraSPARC-I Emulation (JG, MB, DC, SC, PD, MD, ME, GF, TG, DG, RJ, MK, RK, MM, CN, SJNJ, TO, GP, CS, NS, JW, PW), pp. 13–18.
DAC-1995-CaoABDDDDDDFGGGILMMMPPPRRSSSSVWYYZZ #design: CAD Methodology for the Design of UltraSPARC-I Microprocessor at Sun Microsystems Inc (AC, AA, JB, PD, PD, PD, MD, TD, MD, PF, OG, DG, SG, JI, LL, JM, MM, SM, PP, AP, RP, SR, NR, PS, SS, RS, BS, WV, MW, PY, RKY, JZ, GBZ), pp. 19–22.
DAC-1995-MannePBHSMP: Computing the Maximum Power Cycles of a Sequential Circuit (SM, AP, RIB, GDH, FS, EM, MP), pp. 23–28.
DAC-1995-ChangP #power management: Register Allocation and Binding for Low Power (JMC, MP), pp. 29–35.
DAC-1995-FarrahiTS #memory management #segmentation: Memory Segmentation to Exploit Sleep Mode Operation (AHF, GET, MS), pp. 36–41.
DAC-1995-MartinK #behaviour #named #optimisation #power management: Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level (RSM, JPK), pp. 42–47.
DAC-1995-WangH: Boolean Matching for Incompletely Specified Functions (KHW, TH), pp. 48–53.
DAC-1995-WurthEA #algorithm #composition #functional #multi: Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm (BW, KE, KA), pp. 54–59.
DAC-1995-StanionS #synthesis: A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis (TS, CS), pp. 60–64.
DAC-1995-ShenHC #composition #set: Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping (WZS, JDH, SMC), pp. 65–69.
DAC-1995-VaishnavP #logic: Minimizing the Routing Cost During Logic Extraction (HV, MP), pp. 70–75.
DAC-1995-FrezzaLC #design #evaluation: Requirements-Based Design Evaluation (STF, SPL, PKC), pp. 76–81.
DAC-1995-JohnsonB #design: Incorporating Design Schedule Management into a Flow Management System (EWJ, JBB), pp. 82–87.
DAC-1995-AltmeyerSS #framework #generative #modelling: Generating ECAD Framework Code from Abstract Models (JA, BS, MS), pp. 88–93.
DAC-1995-BredenfeldC #design #graph #integration #tool support #using: Tool Integration and Construction Using Generated Graph-Based Design Representations (AB, RC), pp. 94–99.
DAC-1995-LyKMM #behaviour #scheduling #using: Scheduling Using Behavioral Templates (TL, DK, RM, DM), pp. 101–106.
DAC-1995-PotkonjakS #constraints #named: Rephasing: A Transformation Technique for the Manipulation of Timing Constraints (MP, MBS), pp. 107–112.
DAC-1995-DeCastelo-Vide-e-SouzaPP #algorithm #approach #architecture #optimisation #throughput #using: Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming (YGDVeS, MP, ACP), pp. 113–118.
DAC-1995-SparmannLCR #fault #identification #performance #robust: Fast Identification of Robust Dependent Path Delay Faults (US, DL, KTC, SMR), pp. 119–125.
DAC-1995-PomeranzR #logic #on the: On Synthesis-for-Testability of Combinational Logic Circuits (IP, SMR), pp. 126–132.
DAC-1995-VenkataramanHFRCP #agile #fault #simulation #using: Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists (SV, IH, WKF, EMR, SC, JHP), pp. 133–138.
DAC-1995-Chamberlain #logic #parallel #simulation: Parallel Logic Simulation of VLSI Systems (RDC), pp. 139–143.
DAC-1995-WalkerG #algorithm #distributed #execution #parallel #simulation: Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors (PAW, SG), pp. 144–150.
DAC-1995-FrenchLLO #compilation #simulation: A General Method for Compiling Event-Driven Simulations (RSF, MSL, JRL, KO), pp. 151–156.
DAC-1995-ChengL #approach #optimisation: A Transformation-Based Approach for Storage Optimization (WKC, YLL), pp. 158–163.
DAC-1995-WuL: Register Minimization beyond Sharing among Variables (TYW, YLL), pp. 164–169.
DAC-1995-FrankRS #architecture: Constrained Register Allocation in Bus Architectures (EF, SR, MS), pp. 170–175.
DAC-1995-El-MalehMRM #on the #testing: On Test Set Preservation of Retimed Circuits (AHEM, TEM, JR, WM), pp. 176–182.
DAC-1995-RudnickP #generative #search-based #testing: Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation (EMR, JHP), pp. 183–188.
DAC-1995-PanL: Partial Scan with Pre-selected Scan Signals (PP, CLL), pp. 189–194.
DAC-1995-AlpertY #clustering: Spectral Partitioning: The More Eigenvectors, The Better (CJA, SZY), pp. 195–200.
DAC-1995-SawkarT #clustering #multi: Multi-way Partitioning for Minimum Delay for Look-Up Table Based FPGAs (PS, DET), pp. 201–205.
DAC-1995-LiuKCH #approach #clustering #graph #replication #using: Performance-Driven Partitioning Using a Replication Graph Approach (LTL, MTK, CKC, TCH), pp. 206–210.
DAC-1995-SwartzS #scalability #standard: Timing Driven Placement for Large Standard Cell Circuits (WS, CS), pp. 211–215.
DAC-1995-HagenHK #heuristic #layout #quantifier: Quantified Suboptimality of VLSI Layout Heuristics (LWH, DJHH, ABK), pp. 216–221.
DAC-1995-Albrecht #concurrent #configuration management #design #simulation: Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD — CCS7E Processor System Simulation (TWA), pp. 222–227.
DAC-1995-ZepterGM #data flow #design #generative #graph #using: Digital Receiver Design Using VHDL Generation from Data Flow Graphs (PZ, TG, HM), pp. 228–233.
DAC-1995-MalleyD #logic #verification: Logic Verification Methodology for PowerPC Microprocessors (CHM, MD), pp. 234–240.
DAC-1995-DevadasM #optimisation #overview #power management: A Survey of Optimization Techniques Targeting Low Power VLSI Circuits (SD, SM), pp. 242–247.
DAC-1995-ImanP #logic #power management: Logic Extraction and Factorization for Low Power (SI, MP), pp. 248–253.
DAC-1995-LavagnoMSS #design #power management #synthesis: Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool (LL, PCM, AS, ALSV), pp. 254–260.
DAC-1995-ChandnaKBRS #compilation #ram: The Aurora RAM Compiler (AC, CDK, RBB, MR, KAS), pp. 261–266.
DAC-1995-RekhiTL #automation #layout #synthesis: Automatic Layout Synthesis of Leaf Cells (SR, JDT, DHL), pp. 267–272.
DAC-1995-MeijsG: Delayed Frontal Solution for Finite-Element Based Resistance Extraction (NPvdM, AJvG), pp. 273–278.
DAC-1995-AharonGLLMMMS #functional #generative #verification: Test Program Generation for Functional Verification of PowerPC Processors in IBM (AA, DG, ML, YL, YM, CM, MM, GS), pp. 279–285.
DAC-1995-KnappLMM #behaviour #specification #synthesis #validation: Behavioral Synthesis Methodology for HDL-Based Specification and Validation (DK, TL, DM, RM), pp. 286–291.
DAC-1995-BombanaCCHMZ #case study #synthesis: Design-Flow and Synthesis for ASICs: A Case Study (MB, PC, SC, RBH, GM, GZ), pp. 292–297.
DAC-1995-BormannLPV #design #hardware #industrial #model checking: Model Checking in Industrial Hardware Design (JB, JL, MP, GV), pp. 298–303.
DAC-1995-LalgudiP #modelling #named #performance: DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling (KNL, MCP), pp. 304–309.
DAC-1995-DeokarS #fresh look #optimisation: A Fresh Look at Retiming Via Clock Skew Optimization (RBD, SSS), pp. 310–315.
DAC-1995-SinghalPRB: The Validity of Retiming Sequential Circuits (VS, CP, RLR, RKB), pp. 316–321.
DAC-1995-KarkowskiO: Retiming Synchronous Circuitry with Imprecise Delays (IK, RHJMO), pp. 322–326.
DAC-1995-LiuPD #performance #scalability: A Fast State Assignment Procedure for Large FSMs (SL, MP, AMD), pp. 327–332.
DAC-1995-KassabMRT #architecture #fault #functional #simulation: Software Accelerated Functional Fault Simulation for Data-Path Architectures (MK, NM, JR, JT), pp. 333–338.
DAC-1995-KriegerBK #fault #multi #simulation: Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy (RK, BB, MK), pp. 339–344.
DAC-1995-KonukFL #fault #network #performance #simulation: Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks (HK, FJF, TL), pp. 345–351.
DAC-1995-Ribas-XirgoC #analysis #fault #simulation: Analysis of Switch-Level Faults by Symbolic Simulation (LR, JC), pp. 352–357.
DAC-1995-KrauterGWP #synthesis: Transmission Line Synthesis (BK, RG, JW, LTP), pp. 358–363.
DAC-1995-GuptaKTWP #bound: The Elmore Delay as a Bound for RC Trees with Generalized Input Signals (RG, BK, BT, JW, LTP), pp. 364–369.
DAC-1995-Rao #analysis #distributed: Delay Analysis of the Distributed RC Line (VBR), pp. 370–375.
DAC-1995-SilveiraKW #3d #modelling #performance: Efficient Reduced-Order Modeling of Frequency-Dependent Coupling Inductances Associated with 3-D Interconnect Structures (LMS, MK, JW), pp. 376–380.
DAC-1995-MehrotraFS #generative #performance: Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs (SM, PDF, MBS), pp. 381–387.
DAC-1995-MonahanB #evaluation #modelling: Symbolic Modeling and Evaluation of Data Paths (CM, FB), pp. 389–394.
DAC-1995-ParulkarGB #design: Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead (IP, SKG, MAB), pp. 395–401.
DAC-1995-GeloshS #layout #modelling #performance #tool support: Deriving Efficient Area and Delay Estimates by Modeling Layout Tools (DSG, DES), pp. 402–407.
DAC-1995-BernMS #performance: Efficient OBDD-Based Boolean Manipulation in CAD beyond Current Limits (JB, CM, AS), pp. 408–413.
DAC-1995-ReddyKP #framework #novel #synthesis #verification: Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment (SMR, WK, DKP), pp. 414–419.
DAC-1995-JainMF #learning #verification: Advanced Verification Techniques Based on Learning (JJ, RM, MF), pp. 420–426.
DAC-1995-ClarkeGMZ #generative #model checking #performance: Efficient Generation of Counterexamples and Witnesses in Symbolic Model Checking (EMC, OG, KLM, XZ), pp. 427–432.
DAC-1995-KruiskampL #algorithm #named #search-based #synthesis: DARWIN: CMOS Opamp Synthesis by Means of a Genetic Algorithm (WK, DL), pp. 433–438.
DAC-1995-WempleY #analysis #megamodelling #using: Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels (ILW, ATY), pp. 439–444.
DAC-1995-LampaertGS: Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits (KL, GGEG, WMCS), pp. 445–449.
DAC-1995-VinnakotaHS #design #difference: System-Level Design for Test of Fully Differential Analog Circuits (BV, RH, NJS), pp. 450–454.
DAC-1995-LiM #analysis #embedded #performance #using: Performance Analysis of Embedded Software Using Implicit Path Enumeration (YTSL, SM), pp. 456–461.
DAC-1995-ChouB #embedded #fine-grained #scheduling: Interval Scheduling: Fine-Grained Code Scheduling for Embedded Systems (PHC, GB), pp. 462–467.
DAC-1995-NarayanG #generative #interface #process #protocol #using: Interfacing Incompatible Protocols Using Interface Process Generation (SN, DG), pp. 468–473.
DAC-1995-FeldmannF #algorithm #linear #modelling #scalability: Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm (PF, RWF), pp. 474–479.
DAC-1995-TelicheveskyKW #analysis #performance: Efficient Steady-State Analysis Based on Matrix-Free Krylov-Subspace Methods (RT, KSK, JW), pp. 480–484.
DAC-1995-ChouKW #3d #approach #simulation #using: Transient Simulations of Three-Dimensional Integrated Circuit Interconnect Using a Mixed Surface-Volume Approach (MC, TK, JW), pp. 485–490.
DAC-1995-XiD #power management #process: Buffer Insertion and Sizing Under Process Variations for Low Power Clock Distribution (JGX, WWMD), pp. 491–496.
DAC-1995-VittalM #design: Power Optimal Buffered Clock Tree Design (AV, MMS), pp. 497–502.
DAC-1995-VittalM95a #design: Power Distribution Topology Design (AV, MMS), pp. 503–507.
DAC-1995-HuangKT #bound #on the #problem: On the Bounded-Skew Clock and Steiner Routing Problems (DJHH, ABK, CWAT), pp. 508–513.
DAC-1995-SmailagicSAKMS #benchmark #concurrent #design #metric: Benchmarking An Interdisciplinary Concurrent Design Methodology for Electronic/Mechanical Systems (AS, DPS, DA, CK, TLM, JS), pp. 514–519.
DAC-1995-ManciniYB: A Methodology for HW-SW Codesign in ATM (GM, DY, SB), pp. 520–527.
DAC-1995-SilburtPBNDW #behaviour #concurrent #design #hardware #modelling #simulation: Accelerating Concurrent Hardware Design with Behavioural Modelling and System Simulation (AS, IP, JB, SN, MD, GW), pp. 528–533.
DAC-1995-BryantC #diagrams #verification: Verification of Arithmetic Circuits with Binary Moment Diagrams (REB, YAC), pp. 535–541.
DAC-1995-Kimura #verification: Residue BDD and Its Application to the Verification of Arithmetic Circuits (SK), pp. 542–545.
DAC-1995-ZhouB #canonical #equivalence: Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions (ZZ, WB), pp. 546–551.
DAC-1995-MakW #logic #on the: On Optimal Board-Level Routing for FPGA-Based Logic Emulation (WKM, DFW), pp. 552–556.
DAC-1995-LeeW #performance: A Performance and Routability Driven Router for FPGAs Considering Path Delays (YSL, ACHW), pp. 557–561.
DAC-1995-AlexanderR #algorithm: New Performance-Driven FPGA Routing Algorithms (MJA, GR), pp. 562–567.
DAC-1995-WuM #2d #approach #optimisation #orthogonal: Orthogonal Greedy Coupling — A New Optimization Approach to 2-D FPGA Routing (YLW, MMS), pp. 568–573.
DAC-1995-Trimberger #architecture: Effects of FPGA Architecture on FPGA Routing (ST), pp. 574–578.
DAC-1995-SilvaK #design #using #web: The Case for Design Using the World Wide Web (MJS, RHK), pp. 579–585.
DAC-1995-ChiodoGJLHSSS #embedded #source code #synthesis: Synthesis of Software Programs for Embedded Control Applications (MC, PG, AJ, LL, HH, KS, ALSV, ES), pp. 587–592.
DAC-1995-TimmerSMJ #code generation #modelling #scheduling: Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores (AHT, MTJS, JLvM, JAGJ), pp. 593–598.
DAC-1995-LiaoDKTW #embedded #optimisation: Code Optimization Techniques for Embedded DSP Microprocessors (SYL, SD, KK, SWKT, ARW), pp. 599–604.
DAC-1995-BiekerM #constraints #generative #logic programming #self #using: Retargetable Self-Test Program Generation Using Constraint Logic Programming (UB, PM), pp. 605–611.
DAC-1995-Najm #correlation #estimation #feedback: Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits (FNN), pp. 612–617.
DAC-1995-MehtaBOI #estimation #process: Accurate Estimation of Combinational Circuit Activity (HM, MB, RMO, MJI), pp. 618–622.
DAC-1995-NajmZ #process #worst-case: Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits (FNN, MYZ), pp. 623–627.
DAC-1995-MarculescuMP #correlation #estimation #performance: Efficient Power Estimation for Highly Correlated Input Streams (RM, DM, MP), pp. 628–634.
DAC-1995-NajmGH #estimation: Power Estimation in Sequential Circuits (FNN, SG, INH), pp. 635–640.
DAC-1995-CoudertM #problem: New Ideas for Solving Covering Problems (OC, JCM), pp. 641–646.
DAC-1995-LinCCMC #logic #synthesis: Logic Synthesis for Engineering Change (CCL, KCC, SCC, MMS, KTC), pp. 647–652.
DAC-1995-NakamuraY #clustering #logic #matrix #optimisation #scalability: A Partitioning-Based Logic Optimization Method for Large Scale Circuits with Boolean Matrix (YN, TY), pp. 653–657.
DAC-1995-YuguchiNWF #logic #multi: Multi-Level Logic Minimization Based on Multi-Signal Implications (MY, YN, KW, TF), pp. 658–662.
DAC-1995-ChangMC #algorithm #performance #set: An Efficient Algorithm for Local Don’t Care Sets Calculation (SCC, MMS, KTC), pp. 663–667.
DAC-1995-RohfleischWA #analysis #logic #optimisation: Logic Clause Analysis for Delay Optimization (BR, BW, KA), pp. 668–672.
DAC-1995-Bergamaschi #design #problem #question #tool support: Productivity Issues in High-Level Design: Are Tools Solving the Real Problems? (RAB), pp. 674–677.
DAC-1995-GiumaleK #modelling: Information Models of VHDL (CAG, HJK), pp. 678–683.
DAC-1995-StollonP #behaviour #complexity #metric #modelling: Measures of Syntactic Complexity for Modeling Behavioral VHDL (NSS, JDP), pp. 684–689.
DAC-1995-MenezesPP #optimisation: Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (NM, SP, LTP), pp. 690–695.
DAC-1995-LeeT #algorithm #analysis #incremental: An Algorithm for Incremental Timing Analysis (JfL, DTT), pp. 696–701.
DAC-1995-FabbroFCG #modelling #probability #standard #worst-case: An Assigned Probability Technique to Derive Realistic Worst-Case Timing Models of Digital Standard Cells (ADF, BF, LC, CG), pp. 702–706.
DAC-1995-JainBJ #abstraction #automation: Automatic Clock Abstraction from Sequential Circuits (SJ, REB, AJ), pp. 707–711.
DAC-1995-LinJK #optimisation: Hierarchical Optimization of Asynchronous Circuits (BL, GGdJ, TK), pp. 712–717.
DAC-1995-SawasakiYL #implementation: Externally Hazard-Free Implementations of Asynchronous Circuits (MHS, CYC, BL), pp. 718–724.
DAC-1995-VanbekbergenWK #design #validation: A Design and Validation System for Asynchronous Circuits (PV, ARW, KK), pp. 725–730.

Bryan PreasProceedings of the 32nd Design Automation ConferenceDAC, 1995.

Contents (122 items)

Bryan Preas
Proceedings of the 32nd Design Automation Conference
DAC, 1995.