BibSLEIGH — Lawrence_T

Travelled to:

15 × USA
3 × France
3 × Germany

Collaborated with:

X.Li M.W.Beattie A.J.Strojwas P.Li F.Dartu Y.Xu B.Krauter Y.Liu B.Tutuianu P.Gopalakrishnan V.Kheterpal S.R.Nassif H.Zheng J.Le T.Lin R.Arunachalam J.Wang M.Celik H.Schmit V.Rovner S.P.Boyd S.Gupta R.Kay A.Koorapaty R.Gupta J.Willis V.Chandra E.Acar D.Pandini R.D.Blanton K.Rajagopal Z.He N.Menezes S.Pullela C.Patel K.Y.Tong T.Jhaveri S.Yaldiz A.Xu Y.Lu T.Young Y.Xia E.A.Dengi F.Liu M.Fu K.Hsiung I.Nausieda Y.Zhan D.Newmark M.Sharma T.G.Hersan D.Motiani Y.Takegawa A.E.Gamal I.Bolsens A.Broom C.Hamlin P.Magarshack Z.Or-Bach F.Wang G.Keskin A.Phelps J.Rotner G.K.Fedder T.Mukherjee

Talks about:

model (15) analysi (11) interconnect (8) extract (8) circuit (8) induct (8) delay (7) time (7) design (6) analog (6)

Person: Lawrence T. Pileggi

DBLP: Pileggi:Lawrence_T=

Contributed to:

2012

2009

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

1996

1995

Wrote 52 papers:

DAC-2012-WangKPRLFMP #adaptation #design #optimisation #statistics: Statistical design and optimization for adaptive post-silicon tuning of MEMS filters (FW, GK, AP, JR, XL, GKF, TM, LTP), pp. 176–181.
DAC-2009-StrojwasJRP #using: Creating an affordable 22nm node using design-lithography co-optimization (AJS, TJ, VR, LTP), pp. 95–96.
DAC-2009-WangYLP #analysis #parametricity: SRAM parametric failure analysis (JW, SY, XL, LTP), pp. 496–501.
DAC-2007-LiP #correlation #multi #parametricity #performance: Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits (XL, LTP), pp. 928–933.
DAC-2007-WangLP #design #megamodelling: Parameterized Macromodeling for Analog System-Level Design Exploration (JW, XL, LTP), pp. 940–943.
DAC-2006-GopalakrishnanLP #architecture #metric #using: Architecture-aware FPGA placement using metric embedding (PG, XL, LTP), pp. 460–465.
DAC-2006-LiLP #analysis #power management #statistics: Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions (XL, JL, LTP), pp. 103–108.
DAC-2005-KheterpalRHMTSP #design: Design methodology for IC manufacturability based on regular logic-bricks (VK, VR, TGH, DM, YT, AJS, LTP), pp. 353–358.
DAC-2005-XuHLNBP #design #named #nondeterminism #optimisation #robust: OPERA: optimization with ellipsoidal uncertainty for robust analog IC design (YX, KLH, XL, IN, SPB, LTP), pp. 632–637.
DAC-2005-ZhanSLPNS #analysis #statistics: Correlation-aware statistical timing analysis with non-gaussian delay distributions (YZ, AJS, XL, LTP, DN, MS), pp. 77–82.
DATE-2005-LiLLPN #modelling #order #parametricity #performance #reduction #using #variability: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction (PL, FL, XL, LTP, SRN), pp. 958–963.
DAC-2004-GuptaP #evaluation #named: CHIME: coupled hierarchical inductance model evaluation (SG, LTP), pp. 800–805.
DAC-2004-KheterpalSP #architecture: Routing architecture exploration for regular fabrics (VK, AJS, LTP), pp. 204–207.
DAC-2004-LeLP #analysis #correlation #named #statistics: STAC: statistical timing analysis with correlation (JL, XL, LTP), pp. 343–348.
DAC-2004-LiXLGP #approach #simulation: A frequency relaxation approach for analog/RF system-level simulation (XL, YX, PL, PG, LTP), pp. 842–847.
DAC-2004-XuPB #layout #named #optimisation: ORACLE: optimization with recourse of analog circuits including layout extraction (YX, LTP, SPB), pp. 151–154.
DATE-v1-2004-KoorapatyKGFP #logic: Exploring Logic Block Granularity for Regular Fabrics (AK, VK, PG, MF, LTP), pp. 468–473.
DATE-v2-2004-ChandraXSP #design #performance: An Interconnect Channel Design Methodology for High Performance Integrated Circuits (VC, AX, HS, LTP), pp. 1138–1143.
DAC-2003-El-GamalBBHMOP #implementation #performance: Fast, cheap and under control: the next implementation fabric (AEG, IB, AB, CH, PM, ZOB, LTP), pp. 354–355.
DAC-2003-LiLXP #analysis #megamodelling: Analog and RF circuit macromodels for system-level analysis (XL, PL, YX, LTP), pp. 478–483.
DAC-2003-LiP #named #order #reduction: NORM: compact model order reduction of weakly nonlinear systems (PL, LTP), pp. 472–477.
DAC-2003-PileggiSSGKKPRT #trade-off: Exploring regular fabrics to optimize the performance-cost trade-off (LTP, HS, AJS, PG, VK, AK, CP, VR, KYT), pp. 782–787.
DATE-2003-KoorapatyCTPPS #architecture #logic #programmable: Heterogeneous Programmable Logic Block Architectures (AK, VC, KYT, CP, LTP, HS), pp. 11118–11119.
DATE-2003-XuLLP #megamodelling: Noise Macromodel for Radio Frequency Integrated Circuits (YX, XL, PL, LTP), pp. 10150–10155.
DAC-2002-LinBP #2d #modelling #on the: On the efficacy of simplified 2D on-chip inductance models (TL, MWB, LTP), pp. 757–762.
DAC-2002-ZhengP #analysis #modelling #network #symmetry: Modeling and analysis of regular symmetrically structured power/ground distribution networks (HZ, LTP), pp. 395–398.
DATE-2002-AcarNP #framework #parametricity #simulation: A Linear-Centric Simulation Framework for Parametric Fluctuations (EA, SRN, LTP), pp. 568–575.
DATE-2002-LiP #analysis #approach #modelling: A Linear-Centric Modeling Approach to Harmonic Balance Analysis (PL, LTP), pp. 634–639.
DATE-2002-LinBP #3d #modelling #question: On-Chip Inductance Models: 3D or Not 3D? (TL, MWB, LTP), p. 1112.
DATE-2002-PandiniPS #logic #synthesis: Congestion-Aware Logic Synthesis (DP, LTP, AJS), pp. 664–671.
DATE-2002-ZhengPBK #analysis #modelling #scalability: Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses (HZ, LTP, MWB, BK), pp. 628–633.
DAC-2001-ArunachalamBP #analysis #interactive: False Coupling Interactions in Static Timing Analysis (RA, RDB, LTP), pp. 726–731.
DAC-2001-BeattieP #modelling: Inductance 101: Modeling and Extraction (MWB, LTP), pp. 323–328.
DAC-2001-BeattieP01a #modelling: Modeling Magnetic Coupling for On-Chip Interconnect (MWB, LTP), pp. 335–340.
DAC-2001-LuCYP #metric #modelling: Min/max On-Chip Inductance Models and Delay Metrics (YCL, MC, TY, LTP), pp. 341–346.
DATE-2001-BeattieP #performance: Efficient inductance extraction via windowing (MWB, LTP), pp. 430–436.
DAC-2000-ArunachalamRP #analysis #named: TACO: timing analysis with coupling (RA, KR, LTP), pp. 266–269.
DAC-2000-LiuNPS: Impact of interconnect variations on the clock skew of a gigahertz microprocessor (YL, SRN, LTP, AJS), pp. 168–171.
DAC-1999-BeattieP #analysis #modelling: IC Analyses Including Extracted Inductance Models (MWB, LTP), pp. 915–920.
DAC-1999-LiuPS #analysis: Model Order-Reduction of RC(L) Interconnect Including Variational Analysis (YL, LTP, AJS), pp. 201–206.
DAC-1998-DartuP #analysis #named: TETA: Transistor-Level Engine for Timing Analysis (FD, LTP), pp. 595–598.
DAC-1998-KayP #named #probability: PRIMO: Probability Interpretation of Moments for Delay Calculation (RK, LTP), pp. 463–468.
DAC-1998-LiuPS #modelling #named #order: ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models (YL, LTP, AJS), pp. 469–472.
DAC-1997-BeattieP #bound: Bounds for BEM Capacitance Extraction (MWB, LTP), pp. 133–136.
DAC-1997-DartuP #worst-case: Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling (FD, LTP), pp. 46–51.
DAC-1997-HeCP #named: SPIE: Sparse Partial Inductance Extraction (ZH, MC, LTP), pp. 137–140.
DAC-1996-DartuTP #megamodelling #simulation: RC-Interconnect Macromodels for Timing Simulation (FD, BT, LTP), pp. 544–547.
DAC-1996-KrauterXDP #image: A Sparse Image Method for BEM Capacitance Extraction (BK, YX, EAD, LTP), pp. 357–362.
DAC-1996-TutuianuDP #approximate: An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response (BT, FD, LTP), pp. 611–616.
DAC-1995-GuptaKTWP #bound: The Elmore Delay as a Bound for RC Trees with Generalized Input Signals (RG, BK, BT, JW, LTP), pp. 364–369.
DAC-1995-KrauterGWP #synthesis: Transmission Line Synthesis (BK, RG, JW, LTP), pp. 358–363.
DAC-1995-MenezesPP #optimisation: Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization (NM, SP, LTP), pp. 690–695.