Travelled to:2 × USA
Collaborated with:Y.Yen N.Nassif D.H.Hall R.Cvijetic J.Jensen
Talks about:delay (2) chip (2) cpu (2) microprocessor (1) distribut (1) techniqu (1) systemat (1) suitabl (1) perform (1) network (1)
Person: Madhav P. Desai
DBLP: Desai:Madhav_P=
Contributed to:
19981996Wrote 3 papers:
- DAC-1998-NassifDH #modelling #robust #verification
- Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor (NN, MPD, DHH), pp. 230–235.
- DAC-1996-DesaiCJ #cpu #network #performance
- Sizing of Clock Distribution Networks for High Performance CPU Chips (MPD, RC, JJ), pp. 389–394.
- DAC-1996-DesaiY #cpu #design #simulation #using #verification
- A Systematic Technique for Verifying Critical Path Delays in a 300MHz Alpha CPU Design Using Circuit Simulation (MPD, YTY), pp. 125–130.