BibSLEIGH — Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint

Sujan Pandey, Manfred Glesner
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
DAC, 2006.

DAC 2006

@inproceedings{DAC-2006-PandeyG,
	author        = "Sujan Pandey and Manfred Glesner",
	booktitle     = "{Proceedings of the 43rd Design Automation Conference}",
	doi           = "10.1145/1146909.1147078",
	isbn          = "1-59593-381-6",
	pages         = "663--668",
	publisher     = "{ACM}",
	title         = "{Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint}",
	year          = 2006,
}

Sujan Pandey, Manfred GlesnerStatistical on-chip communication bus synthesis and voltage scaling under timing yield constraintDAC, 2006.

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Sujan Pandey, Manfred Glesner
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint
DAC, 2006.