Stem bus$ (all stems)

145 papers:

CASE-2015-CarliDEAV #automation #evaluation #using

Automated evaluation of urban traffic congestion using bus as a probe (RC, MD, NE, BA, AV), pp. 967–972.

DATE-2015-ChenEC #3d #hybrid

Enabling vertical wormhole switching in 3D NoC-bus hybrid systems (CC, ME, SDC), pp. 507–512.

DATE-2015-HuangTTC #architecture

Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects (SYH, MTT, KHHT, WTC), pp. 924–927.

SANER-2015-CosentinoIC #git #repository

Assessing the bus factor of Git repositories (VC, JLCI, JC), pp. 499–503.

CHI-2015-PritchardBVO #how #mobile #performance

How to Drive a London Bus: Measuring Performance in a Mobile and Remote Workplace (GWP, PB, JV, PO), pp. 1885–1894.

HCI-UC-2015-DantecWCM #ecosystem

Cycle Atlanta and OneBusAway: Driving Innovation Through the Data Ecosystems of Civic Computing (CALD, KEW, RJC, EDM), pp. 327–338.

ISMM-2015-HusseinHPV #garbage collection #memory management

Don’t race the memory bus: taming the GC leadfoot (AH, ALH, MP, CAV), pp. 15–27.

CASE-2014-TanHZ #automation #development #validation

Development and validation of an automated steering control system for bus revenue service (HST, JH, WBZ), pp. 31–36.

DATE-2014-JalleKAQC #design #manycore

Bus designs for time-probabilistic multicore processors (JJ, LK, JA, EQ, FJC), pp. 1–6.

DATE-2014-LeeL #3d #gpu #on the #reduction

On GPU bus power reduction with 3D IC technologies (YJL, SKL), pp. 1–6.

CHI-2014-PritchardVBTO #how

Digitally driven: how location based services impact the work practices of London bus drivers (GWP, JV, PB, LT, PO), pp. 3617–3626.

ICEIS-v1-2014-TitoRSFTS #information management #named #recommendation

RecRoute — A Bus Route Recommendation System Based on Users’ Contextual Information (AdOT, ARRR, LMdS, LAVF, PRT, ACS), pp. 357–366.

DATE-2013-FakihGFR #analysis #architecture #model checking #performance #towards #using

Towards performance analysis of SDFGs mapped to shared-bus architectures using model-checking (MF, KG, MF, AR), pp. 1167–1172.

CHI-2013-YooZH #co-evolution #design

Probing bus stop for insights on transit co-design (DY, JZ, TH), pp. 409–418.

VMCAI-2013-CruanesHOS #integration #tool support

Tool Integration with the Evidential Tool Bus (SC, GH, SO, NS), pp. 275–294.

DATE-2012-DonnoFSPB #energy #performance

Mechatronic system for energy efficiency in bus transport (MD, AF, AS, PP, AB), pp. 342–343.

ICEIS-v2-2012-KitanoST #community #framework #lightweight #web

Lightweight Web Application Framework and Its Application — Helping Improve Community Bus Timetables after Japan Earthquake (YK, HS, AT), pp. 252–257.

DAC-2011-MaYW #algorithm

An optimal algorithm for layer assignment of bus escape routing on PCBs (QM, EFYY, MDFW), pp. 176–181.

DATE-2011-AgyekumN #communication #hardware #robust

A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication (MYA, SMN), pp. 1370–1375.

DATE-2011-PenolazziSH #energy #multi #performance #predict

Predicting bus contention effects on energy and performance in multi-processor SoCs (SP, IS, AH), pp. 1196–1199.

DATE-2011-ShahRK #bound #latency #performance

Priority division: A high-speed shared-memory bus arbitration with bounded latency (HS, AR, AK), pp. 1497–1500.

CHI-2011-ZimmermanTGYHATHS #co-evolution #design

Field trial of Tiramisu: crowd-sourcing bus arrival times to spur co-design (JZ, AT, CG, DY, CH, RA, NRT, YH, AS), pp. 1677–1686.

HCI-MIIE-2011-KimHJHMJ #analysis #behaviour #using #video

Analysis of Low-Floor Bus Passengers’ Behavior Patterns Using Video Observation (JYK, HH, BSJ, BHH, YJM, YGJ), pp. 391–400.

HCI-MIIE-2011-LinH #adaptation #performance #predict

Predicting the Effects of Time-Gaps for Adaptive Cruise Control (ACC) on Bus Driver Performance (BTWL, SLH), pp. 435–443.

SEKE-2011-BhattacharyaCSK #enterprise #using

Dynamic Service Choreography using Context Aware Enterprise Service Bus (SB, JC, SS, AK), pp. 319–324.

LCTES-2011-ChattopadhyayR #multi

Static bus schedule aware scratchpad allocation in multiprocessors (SC, AR), pp. 11–20.

CAV-2011-MullerP #hardware #interface #verification

Complete Formal Hardware Verification of Interfaces for a FlexRay-Like Bus (CAM, WJP), pp. 633–648.

DAC-2010-YanC

Two-sided single-detour untangling for bus routing (JTY, ZWC), pp. 206–211.

DATE-2010-DasMZC #detection #hardware #information management #memory management

Detecting/preventing information leakage on the memory bus due to malicious hardware (AD, GM, JZ, ANC), pp. 861–866.

TACAS-2010-AvnitSP #automation #named #protocol #synthesis

ACS: Automatic Converter Synthesis for SoC Bus Protocols (KA, AS, JP), pp. 343–348.

CHI-2010-FerrisWB #named #realtime

OneBusAway: results from providing real-time arrival information for public transit (BF, KW, AB), pp. 1807–1816.

HPCA-2010-UdipiMB #energy #network #scalability #towards

Towards scalable, energy-efficient, bus-based on-chip networks (ANU, NM, RB), pp. 1–12.

DAC-2009-KongYW #automation

Automatic bus planner for dense PCBs (HK, TY, MDFW), pp. 326–331.

DAC-2009-WangCSC #graph #power management #synthesis #using

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications (RW, NCC, BS, CKC), pp. 166–171.

DAC-2009-ZengZNGGS #optimisation #scheduling #using

Scheduling the FlexRay bus using optimization techniques (HZ, WZ, MDN, AG, PG, ALSV), pp. 874–877.

DATE-2009-MollCRB #modelling #performance #protocol #using

Fast and accurate protocol specific bus modeling using TLM 2.0 (HWMvM, HC, VR, MB), pp. 316–319.

DATE-2009-SanderGRBM #communication

Priority-based packet communication on a bus-shaped structure for FPGA-systems (OS, BG, CR, JB, KDMG), pp. 178–183.

DATE-2009-SuCGSP #memory management #named #operating system

SecBus: Operating System controlled hierarchical page-based memory bus protection (LS, SC, PG, CS, RP), pp. 570–573.

SAC-2009-AraujoS #embedded #integration #web #web service

The device service bus: a solution for embedded device integration through web services (GMA, FS), pp. 185–189.

DAC-2008-LinSH #multi #realtime

A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer (YTL, WCS, IJH), pp. 862–865.

DAC-2008-RoyKM #hardware

Protecting bus-based hardware IP by secret sharing (JAR, FK, ILM), pp. 846–851.

DATE-2008-ApostolakisGPP #functional #multi #self #symmetry

Functional Self-Testing for Bus-Based Symmetric Multiprocessors (AA, DG, MP, AMP), pp. 1304–1309.

DATE-2008-ChenDC #encryption #operating system

Operating System Controlled Processor-Memory Bus Encryption (XC, RPD, ANC), pp. 1154–1159.

DATE-2008-DuanK #energy #performance

Energy Efficient and High Speed On-Chip Ternary Bus (CD, SPK), pp. 515–518.

DATE-2008-PandeyD #architecture #memory management #optimisation

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs (SP, RD), pp. 206–211.

SIGAda-2008-SwardW #architecture #enterprise #multi #using

A multi-language service-oriented architecture using an enterprise service bus (RES, KJW), pp. 85–90.

SAC-2008-SriplakichBG #collaboration #experience #modelling #re-engineering #requirements #scalability

Collaborative software engineering on large-scale models: requirements and experience in ModelBus (PS, XB, MPG), pp. 674–681.

DAC-2007-GuHY #distributed #embedded #model checking #optimisation

Optimization of Static Task and Bus Access Schedules for Time-Triggered Distributed Embedded Systems with Model-Checking (ZG, XH, MY), pp. 294–299.

DAC-2007-JiangHS #design #difference

A New Twisted Differential Line Structure in Global Bus Design (ZJ, SH, WS), pp. 180–183.

DATE-2007-LeGB #pervasive #verification

Formal verification of a pervasive interconnect bus system in a high-performance microprocessor (TL, TG, JB), pp. 219–224.

DATE-2007-PopPEP #distributed #embedded #optimisation

Bus access optimisation for FlexRay-based distributed embedded systems (TP, PP, PE, ZP), pp. 51–56.

ICSM-2007-OezbekP #comprehension #documentation #named #source code

JTourBus: Simplifying Program Understanding by Documentation that Provides Tours Through the Source Code (CO, LP), pp. 64–73.

SAC-2007-ChenTL

A priority assignment strategy of processing elements over an on-chip bus (YSC, SJT, SWL), pp. 1176–1180.

SAC-2007-HwangPJ #analysis #implementation #performance

An implementation and performance analysis of slave-side arbitration schemes for the ML-AHB BusMatrix (SYH, HJP, KSJ), pp. 1545–1551.

DAC-2006-BrahmbhattZWQ #adaptation #algorithm #encoding #hybrid #power management #using

Low-power bus encoding using an adaptive hybrid algorithm (ARB, JZ, QW, QQ), pp. 987–990.

DAC-2006-ElbazTSGBM #encryption

A parallelized way to provide data encryption and integrity checking on a processor-memory bus (RE, LT, GS, PG, MB, AM), pp. 506–509.

DAC-2006-KlingaufGBPB #modelling #named #transaction

GreenBus: a generic interconnect fabric for transaction level modelling (WK, RG, OB, PP, MB), pp. 905–910.

DAC-2006-PandeyG #communication #constraints #scalability #statistics #synthesis

Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint (SP, MG), pp. 663–668.

DAC-2006-TanimotoYNH #realtime #using

A real time budgeting method for module-level-pipelined bus based system using bus scenarios (TT, SY, AN, TH), pp. 37–42.

DATE-2006-LaMeresK #encoding #induction

Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission (BJL, SPK), pp. 522–527.

DATE-2006-RossiSM #analysis

Analysis of the impact of bus implemented EDCs on on-chip SSN (DR, CS, CM), pp. 59–64.

DATE-2006-SchirnerD #analysis #modelling #transaction

Quantitative analysis of transaction level models for the AMBA bus (GS, RD), pp. 230–235.

DATE-2006-SekarLRD #adaptation #configuration management

Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms (KS, KL, AR, SD), pp. 728–733.

DATE-2006-UmKHKCKEK #design #modelling

A systematic IP and bus subsystem modeling for platform-based system design (JU, WCK, SH, YTK, KMC, JTK, SKE, TK), pp. 560–564.

DATE-2006-WangXVI #analysis #optimisation

On-chip bus thermal analysis and optimization (FW, YX, NV, MJI), pp. 850–855.

SAC-2006-GuesmiR #design #embedded #implementation #realtime

Design and implementation of a real-time notification service within the context of embedded ORB and the CAN bus (TG, HR), pp. 773–777.

DAC-2005-PasrichaDBB #architecture #automation #communication #synthesis

Floorplan-aware automated synthesis of bus-based communication architectures (SP, NDD, EB, MBR), pp. 565–570.

DAC-2005-SuhKL #architecture

Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs (TS, DK, HHSL), pp. 553–558.

DATE-2005-ElbazTSGABBR #bibliography #encryption #hardware

Hardware Engines for Bus Encryption: A Survey of Existing Techniques (RE, LT, GS, PG, CA, MB, CB, JBR), pp. 40–45.

DATE-2005-GangwarBPK #architecture #clustering #evaluation

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures (AG, MB, PRP, AK), pp. 730–735.

DATE-2005-KaulSBMA #design #fault

DVS for On-Chip Bus Designs Based on Timing Error Correction (HK, DS, DB, TNM, TMA), pp. 80–85.

DATE-2005-KimKKSCCKE #architecture #modelling #performance #transaction

Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture (YTK, TK, YK, CS, EYC, KMC, JTK, SKE), pp. 138–139.

DATE-2005-SrinivasanLV #architecture #clustering

Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures (SS, LL, NV), pp. 218–223.

ITiCSE-2005-Alvim

Taking the bus in the information highway system (DA), p. 403.

SAC-2005-BelmontePTF #coordination

Agent coordination for bus fleet management (MVB, JLPdlC, FTR, AF), pp. 462–466.

DAC-2004-ContiCVOT #algorithm #analysis #performance

Performance analysis of different arbitration algorithms of the AMBA AHB bus (MC, MC, GBV, SO, CT), pp. 618–621.

DAC-2004-DeogunRSB #encoding #reduction

Leakage-and crosstalk-aware bus encoding for total power reduction (HD, RRR, DS, DB), pp. 779–782.

DATE-DF-2004-NeffeRSWRM #energy #estimation #modelling #power management #smarttech

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards (UN, KR, CS, RW, ER, AM), pp. 300–305.

DATE-v1-2004-SeceleanuW #aspect-oriented #design #visual notation

Aspects of Formal and Graphical Design of a Bus System (TS, TW), pp. 396–403.

DATE-v1-2004-ShinKCCKE #architecture #design #performance

Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design (CS, YTK, EYC, KMC, JTK, SKE), pp. 352–357.

DATE-v1-2004-ThepayasuwanD #architecture #layout #synthesis

Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip (NT, AD), pp. 108–113.

DATE-v1-2004-WongT #configuration management #encoding #power management

Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus (SKW, CYT), pp. 130–135.

DATE-v2-2004-DengW #algorithm

Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus (LD, MDFW), pp. 1104–1109.

DATE-v2-2004-GuptaK #performance #statistics

A Fast Word-Level Statistical Estimator of Intra-Bus Crosstalk (SG, SK), pp. 1110–1115.

DATE-v2-2004-LampropoulosAR #using

Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique (ML, BMAH, PMR), pp. 1372–1373.

DATE-v2-2004-LiverisB #design #interface #power management #synthesis

Power Aware Interface Synthesis for Bus-Based SoC Design (NDL, PB), pp. 864–869.

ASPLOS-2004-ZhuangZP #framework #information management #named

HIDE: an infrastructure for efficiently protecting information leakage on the address bus (XZ, TZ, SP), pp. 72–84.

DAC-2003-BashirullahLC #adaptation #design #power management

Low-power design methodology for an on-chip bus with adaptive bandwidth capability (RB, WL, RKCI), pp. 628–633.

DAC-2003-MeyerowitzPS #policy #realtime #scheduling

A tool for describing and evaluating hierarchical real-time bus scheduling policies (TM, CP, ALSV), pp. 312–317.

DATE-2003-CaldariCCCOPT #analysis

System-Level Power Analysis Methodology Applied to the AMBA AHB Bus (MC, MC, MC, PC, SO, LP, CT), pp. 20032–20039.

DATE-2003-CaldariCCCPT #architecture #modelling #transaction #using

Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0 (MC, MC, MC, SC, LP, CT), pp. 20026–20031.

DATE-2003-DragoFMPP #architecture #embedded #estimation #performance #tuple

Estimation of Bus Performance for a Tuplespace in an Embedded Architecture (ND, FF, MM, GP, MP), pp. 20188–20195.

DATE-2003-HuangCW #nondeterminism

Global Wire Bus Configuration with Minimum Delay Uncertainty (LDH, HMC, DFW), pp. 10050–10055.

DATE-2003-OgawaNCSWNST #approach #architecture #optimisation #transaction

A Practical Approach for Bus Architecture Optimization at Transaction Level (OO, SBdN, PC, KS, YW, HN, TS, YT), pp. 20176–20181.

DATE-2003-RoychoudhuryMK #debugging #protocol #using

Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol (AR, TM, SRK), pp. 10828–10833.

DATE-2003-RyuM #automation #design #generative #multi

Automated Bus Generation for Multiprocessor SoC Design (KKR, VJM), pp. 10282–10289.

CADE-2002-ZimmerK #distributed #reasoning

System Description: The MathWeb Software Bus for Distributed Mathematical Reasoning (JZ, MK), pp. 139–143.

DAC-2001-HenkelL #adaptation #design #named #power management

A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs (JH, HL), pp. 744–749.

DAC-2001-ShinS #design #power management

Coupling-Driven Bus Design for Low-Power Application-Specific Systems (YS, TS), pp. 750–753.

DAC-2001-YangPT #bound

Improving Bus Test Via IDDT and Boundary Scan (SYY, CAP, MTA), pp. 307–312.

DATE-2001-YeungHMMZ #integration #question #standard #what

Standard bus vs. bus wrapper: what is the best solution for future SoC integration? (CY, AH, GM, JM, JZ), pp. 776–777.

DAC-2000-BorosRP #configuration management #multi

High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system (VEB, ADR, SP), pp. 221–226.

DAC-2000-ChangKC #encoding #memory management #power management

Bus encoding for low-power high-performance memory systems (NC, KK, JC), pp. 800–805.

DAC-2000-GoelL #verification

Formal verification of an IBM CoreConnect processor local bus arbiter core (AG, WRL), pp. 196–200.

DATE-2000-BenabdenebiMM #configuration management #named #scalability

CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip (MB, WM, MM), pp. 141–145.

DATE-2000-HenkeGV #design #estimation #performance

Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design (JH, TG, FV), pp. 333–338.

DATE-2000-HiroseY #reduction

A Bus Delay Reduction Technique Considering Crosstalk (KH, HY), pp. 441–445.

DATE-2000-HsiehP #architecture #optimisation

Architectural Power Optimization by Bus Splitting (CTH, MP), pp. 612–616.

DATE-2000-LyseckyVG #latency

Techniques for Reducing Read Latency of Core Bus Wrappers (RLL, FV, TG), pp. 84–91.

DATE-2000-MetraFR #online #testing

On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values (CM, MF, BR), p. 763.

DATE-2000-PopEP #analysis #distributed #embedded #optimisation #scheduling

Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis (PP, PE, ZP), pp. 567–574.

LCTES-2000-ChildersN #memory management #order #power management #transaction

Reordering Memory Bus Transactions for Reduced Power Consumption (BRC, TN), pp. 146–161.

LCTES-2000-JeonKHK #corba #embedded #fault tolerance

A Fault Tolerance Extension to the Embedded CORBA for the CAN Bus Systems (GJ, THK, SH, SK), pp. 114–133.

DATE-1998-BeniniMSMS #encoding #optimisation

Address Bus Encoding Techniques for System-Level Power Optimization (LB, GDM, DS, EM, CS), pp. 861–866.

EDOC-1998-FerayBDT #object-oriented

An object-oriented software bus for supervision systems, based on DCOM (AF, FB, VD, FT), pp. 263–273.

SAC-1998-Kimm #2d #configuration management #pipes and filters #problem

Two dimensional maximal elements problem on a reconfigurable optical pipelined bus system (HK), pp. 623–627.

CAV-1998-EmersonN #protocol #verification

Verification of Parameterized Bus Arbitration Protocol (EAE, KSN), pp. 452–463.

HPCA-1997-DahlgrenL #multi

Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors (FD, AL), pp. 14–23.

HPDC-1997-SteeleDKL #interface #multi #network

A Bus-Efficient Low-Latency Network Interface for the PDSS Multicomputer (CSS, JTD, JK, CL), pp. 213–222.

DAC-1996-DasguptaK #process #reliability

Electromigration Reliability Enhancement via Bus Activity Distribution (AD, RK), pp. 353–356.

FME-1996-BoigelotG #analysis #model checking #protocol #using

Model Checking in Practice: An Analysis of the ACCESS.bus Protocol using SPIN (BB, PG), pp. 465–478.

HPCA-1996-ElGindySSSS #configuration management #multi #named #network

RMB — A Reconfigurable Multiple Bus Network (HAE, AKS, HS, HS, AS), pp. 108–117.

HPCA-1996-KarlssonS #clustering #evaluation #multi #performance

Performance Evaluation of a Cluster-Based Multiprocessor Built from ATM Switches and Bus-Based Multiprocessor Servers (MK, PS), pp. 4–13.

HPCA-1996-LandinD #multi

Bus-Based COMA — Reducing Traffic in Shared-Bus Multiprocessors (AL, FD), pp. 95–105.

HPCA-1996-TakahashiTKS #multi #protocol

A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor (MT, HT, EK, SS), pp. 314–322.

CAV-1996-BengtssonGKLLPY #protocol #using #verification

Verification of an Audio Protocol with Bus Collision Using UPPAAL (JB, WODG, KJK, KGL, FL, PP, WY), pp. 244–256.

DAC-1995-FrankRS #architecture

Constrained Register Allocation in Bus Architectures (EF, SR, MS), pp. 170–175.

HPCA-1995-AndersonB #multi #performance

Two Techniques for Improving Performance on Bus-Based Multiprocessors (CA, JLB), pp. 264–275.

HPCA-1995-CitronR #using

Creating a Wider Bus Using Caching Techniques (DC, LR), pp. 90–99.

EDAC-1994-HaberlK #interface #maintenance #standard

Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface (OFH, TK), pp. 220–225.

EDAC-1994-IkedaA

A Reduced-swing Data Transmission Scheme for Resistive Bus Lines in VSLIs (MI, KA), pp. 546–550.

EDAC-1994-NarayanG #interface #synthesis

Synthesis of System-Level Bus Interfaces (SN, DG), pp. 395–399.

FME-1994-Seidel #case study #refinement #specification

Case Study: Specification and Refinement of the PI-Bus (KS), pp. 532–546.

SEKE-1994-DuranteSV #protocol #specification

A LOTOS specification of the SERCOS field-bus protocol (LD, RS, AV), pp. 139–147.

TOOLS-EUROPE-1994-Migeon #database #independence #relational

A Dossier Server: an Independent Service Bus Between Object Applications and Relational Data Bases (MM), pp. 455–465.

SOSP-1993-OkiPSS #architecture #distributed

The Information Bus — An Architecture for Extensible Distributed Systems (BMO, MP, AS, DS), pp. 58–68.

DAC-1992-LeongB #automation #generative #interface #modelling

The Automatic Generation of Bus-Interface Models (YHL, WPB), pp. 634–637.

TOOLS-EUROPE-1992-Berre #case study #experience #integration #object-oriented

Experiences from System Integration through an OO Software Bus (AJB), pp. 33–45.

DAC-1989-VanHornR #architecture #automation #design #experience #framework

Experience with D-BUS Architecture for a Design Automation Framework (ECV, RRR), pp. 209–214.

CAiSE-1989-Skjellaug #interface #multi #named

IB — An Information Bus: A Multilayered Information Base Interface for Remote Applications (BS).

ASPLOS-1989-EggersK #parallel #performance #source code

The Effect of Sharing on the Cache and Bus Performance of Parallel Programs (SJE, RHK), pp. 257–270.

DAC-1984-TsengS #design #named

Emerald: A bus style designer (CJT, DPS), pp. 315–321.

DAC-1983-OdawaraIK #clustering

Partitioning and placement technique for bus-structured PWB (GO, KI, TK), pp. 449–456.

DAC-1982-LieH #layout

A bus router for IC layout (ML, CSH), pp. 129–132.

DAC-1981-TsengS #modelling #synthesis

The modeling and synthesis of bus systems (CJT, DPS), pp. 471–478.