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Travelled to:
1 × USA
2 × Germany
Collaborated with:
B.Vermeulen R.Drechsler M.Glesner
Talks about:
synthesi (2) bus (2) architectur (1) constraint (1) transient (1) techniqu (1) communic (1) statist (1) automot (1) analysi (1)

Person: Sujan Pandey

DBLP DBLP: Pandey:Sujan

Contributed to:

DATE 20142014
DATE 20082008
DAC 20062006

Wrote 3 papers:

DATE-2014-PandeyV #analysis #fault #safety
Transient errors resiliency analysis technique for automotive safety critical applications (SP, BV), pp. 1–4.
DATE-2008-PandeyD #architecture #memory management #optimisation
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs (SP, RD), pp. 206–211.
DAC-2006-PandeyG #communication #constraints #scalability #statistics #synthesis
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint (SP, MG), pp. 663–668.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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