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Travelled to:
1 × France
1 × Germany
Collaborated with:
M.Barcelos R.A.d.L.Reis S.V.Silva F.R.Wagner M.O.Johann R.Reis S.Bampi
Talks about:
implement (1) algorithm (1) rijndael (1) multipli (1) pipelin (1) design (1) occup (1) fpgas (1) devic (1) veri (1)

Person: Alex Panato

DBLP DBLP: Panato:Alex

Contributed to:

DATE DF 20042004
DATE 20032003

Wrote 2 papers:

DATE-DF-2004-PanatoSWJRB #design #multi #pipes and filters
Design of Very Deep Pipelined Multipliers for FPGAs (AP, SVS, FRW, MOJ, RR, SB), pp. 52–57.
DATE-2003-PanatoBR #algorithm
A Low Device Occupation IP to Implement Rijndael Algorithm (AP, MB, RAdLR), pp. 20020–20025.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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