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Travelled to:
1 × USA
2 × France
Collaborated with:
M.R.Guthaus G.Wilke M.S.Reorda M.Violante C.Meinhardt A.Panato S.V.Silva F.R.Wagner M.O.Johann S.Bampi
Talks about:
processor (1) multipli (1) uniform (1) program (1) pogramm (1) pipelin (1) system (1) linear (1) insert (1) design (1)

Person: Ricardo Reis

DBLP DBLP: Reis:Ricardo

Contributed to:

DAC 20102010
DATE 20092009
DATE DF 20042004

Wrote 3 papers:

DAC-2010-GuthausWR #linear #optimisation #programming
Non-uniform clock mesh optimization with linear programming buffer insertion (MRG, GW, RR), pp. 74–79.
DATE-2009-ReordaVMR #embedded #low cost
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips (MSR, MV, CM, RR), pp. 352–357.
DATE-DF-2004-PanatoSWJRB #design #multi #pipes and filters
Design of Very Deep Pipelined Multipliers for FPGAs (AP, SVS, FRW, MOJ, RR, SB), pp. 52–57.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.