BibSLEIGH — Sergio

Travelled to:

3 × USA
4 × France
4 × Germany

Collaborated with:

M.Shafique J.Henkel B.Zatt S.V.Silva F.Sampaio A.Girardi J.H.Choi L.V.Agostini M.R.Boschetti I.S.Silva A.M.S.Adário E.L.Roehe C.M.Diniz F.V.Dalcin F.L.Walter A.Panato F.R.Wagner M.O.Johann R.Reis

Talks about:

video (8) architectur (6) code (6) multiview (4) effici (4) pipelin (3) motion (3) memori (3) energi (3) dispar (3)

Person: Sergio Bampi

DBLP: Bampi:Sergio

Contributed to:

2015

2014

2013

2012

2011

2005

2004

2003

1999

Wrote 12 papers:

DATE-2015-DinizSDBH #architecture #hardware #performance #standard #video: A deblocking filter hardware architecture for the high efficiency video coding standard (CMD, MS, FVD, SB, JH), pp. 1509–1514.
DATE-2014-SampaioSZBH #architecture #distributed #energy #memory management #named #performance #video: dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding (FS, MS, BZ, SB, JH), pp. 1–6.
DATE-2013-SampaioZSABH #energy #estimation #memory management #multi #video: Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding (FS, BZ, MS, LVA, SB, JH), pp. 665–670.
DAC-2012-ShafiqueZWBH #adaptation #memory management #multi #power management #video: Adaptive power management of on-chip video memory for multiview video coding (MS, BZ, FLW, SB, JH), pp. 866–875.
DAC-2011-ZattSSABH #adaptation #energy #estimation #multi #runtime #video: Run-time adaptive energy-aware motion and disparity estimation in multiview video coding (BZ, MS, FS, LVA, SB, JH), pp. 1026–1031.
DATE-2011-ZattSBH #architecture #estimation #hardware #parallel #pipes and filters #throughput #video: Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding (BZ, MS, SB, JH), pp. 1448–1453.
DATE-2005-SilvaB #architecture #design #pipes and filters #throughput #trade-off: Area and Throughput Trade-Offs in the Design of Pipelined Discrete Wavelet Transform Architectures (SVS, SB), pp. 32–37.
DATE-DF-2004-BoschettiSB #architecture #configuration management #image #runtime: A Run-Time Reconfigurable Datapath Architecture for Image Processing Applications (MRB, ISS, SB), pp. 242–247.
DATE-DF-2004-PanatoSWJRB #design #multi #pipes and filters: Design of Very Deep Pipelined Multipliers for FPGAs (AP, SVS, FRW, MOJ, RR, SB), pp. 52–57.
DATE-2003-GirardiB #automation #generative #layout #named: LIT — An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks (AG, SB), pp. 11106–11107.
DAC-1999-AdarioRB #architecture #configuration management #image: Dynamically Reconfigurable Architecture for Image Processor Applications (AMSA, ELR, SB), pp. 623–628.
DATE-1999-ChoiB #array #design: OTA Amplifiers Design on Digital Sea-of-Transistors Array (JHC, SB), pp. 776–777.