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Travelled to:
1 × Israel
3 × USA
Collaborated with:
R.E.Bryant M.N.Velev K.L.Nelson S.Jain
Talks about:
simul (2) level (2) superscalar (1) sequenti (1) abstract (1) hardwar (1) circuit (1) automat (1) acceler (1) symbol (1)

Person: Alok Jain

DBLP DBLP: Jain:Alok

Contributed to:

CAV 19971997
DAC 19971997
DAC 19951995
DAC 19911991

Wrote 4 papers:

CAV-1997-VelevBJ #array #memory management #modelling #performance #simulation
Efficient Modeling of Memory Arrays in Symbolic Simulation (MNV, REB, AJ), pp. 388–399.
DAC-1997-NelsonJB #execution #verification
Formal Verification of a Superscalar Execution Unit (KLN, AJ, REB), pp. 161–166.
DAC-1995-JainBJ #abstraction #automation
Automatic Clock Abstraction from Sequential Circuits (SJ, REB, AJ), pp. 707–711.
DAC-1991-JainB #hardware #simulation
Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators (AJ, REB), pp. 219–222.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.