Travelled to:1 × France
2 × USA
Collaborated with:D.Z.Pan J.Hu R.N.Mahapatra A.Chakraborty G.Ganesan
Talks about:clock (4) tree (2) skew (2) synthesi (1) variabl (1) analysi (1) robust (1) design (1) reduc (1) optim (1)
Person: Anand Rajaram
DBLP: Rajaram:Anand
Contributed to:
2009
20082004Wrote 3 papers:
- DATE-2009-ChakrabortyGRP #analysis #optimisation
- Analysis and optimization of NBTI induced clock skew in gated clock trees (AC, GG, AR, DZP), pp. 296–299.
- DAC-2008-RajaramP #design #robust #synthesis
- Robust chip-level clock tree synthesis for SOC designs (AR, DZP), pp. 720–723.
- DAC-2004-RajaramHM #variability
- Reducing clock skew variability via cross links (AR, JH, RNM), pp. 18–23.