BibSLEIGH corpus
BibSLEIGH tags
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × France
2 × USA
Collaborated with:
D.Z.Pan J.Hu R.N.Mahapatra A.Chakraborty G.Ganesan
Talks about:
clock (4) tree (2) skew (2) synthesi (1) variabl (1) analysi (1) robust (1) design (1) reduc (1) optim (1)

Person: Anand Rajaram

DBLP DBLP: Rajaram:Anand

Contributed to:

DATE 20092009
DAC 20082008
DAC 20042004

Wrote 3 papers:

DATE-2009-ChakrabortyGRP #analysis #optimisation
Analysis and optimization of NBTI induced clock skew in gated clock trees (AC, GG, AR, DZP), pp. 296–299.
DAC-2008-RajaramP #design #robust #synthesis
Robust chip-level clock tree synthesis for SOC designs (AR, DZP), pp. 720–723.
DAC-2004-RajaramHM #variability
Reducing clock skew variability via cross links (AR, JH, RNM), pp. 18–23.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.