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Travelled to:
2 × France
Collaborated with:
W.Rosenstiel M.Krause O.Bringmann G.Tabanoglu
Talks about:
softwar (2) time (2) interconnect (1) architectur (1) processor (1) autosar (1) analysi (1) static (1) compon (1) advanc (1)

Person: André Hergenhan

DBLP DBLP: Hergenhan:Andr=eacute=

Contributed to:

DATE 20072007
DATE 20002000

Wrote 2 papers:

DATE-2007-KrauseBHTR #component #simulation
Timing simulation of interconnected AUTOSAR software-components (MK, OB, AH, GT, WR), pp. 474–479.
DATE-2000-HergenhanR #analysis #architecture #embedded
Static Timing Analysis of Embedded Software on Advanced Processor Architectures (AH, WR), pp. 552–559.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.