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Travelled to:
4 × USA
5 × Germany
9 × France
Collaborated with:
W.Rosenstiel A.Viehl S.Stattelmann J.Schnerr M.Pressler T.Schönwald J.Zimmermann C.Gerum A.Siebenborn C.Menn A.Braun D.Lettnin J.M.Kühn D.Peterson H.Amano G.Gebhard C.Cullmann M.Krause A.Hergenhan G.Tabanoglu W.Klingauf R.Günzel P.Parfuntseu M.Burton W.Ecker D.Müller-Gritschneder A.Burger A.Crone C.Chevallaz B.Dickman V.Esen M.Rohleder A.Gerstlauer A.Goyal P.Sasidharan S.Singh T.Nirmaier M.Harrant G.Pelz M.Müller A.G.Braun J.Gerlach D.Nienhüser J.M.Zöllner K.Knoedler J.Steinmann S.Laversanne S.Jones A.Huss E.Kural D.Sánchez J.Oetjens N.Bannow M.Becker M.Chaari S.Chakraborty R.Drechsler K.Grüttner T.Kruse C.Kuznik H.M.Le M.Mauderer W.Müller F.Poppen H.Post S.Reiter S.Roth U.Schlichtmann A.v.Schwerin B.Tabacaru
Talks about:
simul (10) level (7) softwar (6) perform (5) analysi (5) system (5) multi (4) accur (4) prototyp (3) automot (3)

Person: Oliver Bringmann

DBLP DBLP: Bringmann:Oliver

Contributed to:

DATE 20152015
CBSE 20142014
DAC 20142014
DATE 20142014
DATE 20132013
DATE 20122012
DAC 20112011
DATE 20112011
DATE 20102010
DATE 20092009
DAC 20082008
DATE 20072007
DAC 20062006
DATE 20062006
DATE 20052005
DATE v1 20042004
DATE 20002000
DATE 19981998

Wrote 24 papers:

DATE-2015-BringmannEGGMSS #generative #prototype #simulation
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems (OB, WE, AG, AG, DMG, PS, SS), pp. 1698–1707.
DATE-2015-GerumBR #gpu #performance #simulation
Source level performance simulation of GPU cores (CG, OB, WR), pp. 217–222.
DATE-2015-KuhnPABR
Spatial and temporal granularity limits of body biasing in UTBB-FDSOI (JMK, DP, HA, OB, WR), pp. 876–879.
CBSE-2014-PresslerVBR #component #deployment #embedded #estimation #execution
Execution cost estimation for software deployment in component-based embedded systems (MP, AV, OB, WR), pp. 123–128.
DAC-2014-OetjensBBBBCCDEGKKLM0MPPRRRSSTV #challenge #evaluation #prototype #research #safety #state of the art #using
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges (JHO, NB, MB, OB, AB, MC, SC, RD, WE, KG, TK, CK, HML, MM, WM, DMG, FP, HP, SR, WR, SR, US, AvS, BAT, AV), p. 6.
DATE-2014-NirmaierBHVBRP #assessment #robust
Mission profile aware robustness assessment of automotive power devices (TN, AB, MH, AV, OB, WR, GP), pp. 1–6.
DATE-2013-SchonwaldVBR #deployment #memory management
Shared memory aware MPSoC software deployment (TS, AV, OB, WR), pp. 1771–1776.
DATE-2012-KnoedlerSLJHKSBZ #energy
Optimal energy management and recovery for FEV (KK, JS, SL, SJ, AH, EK, DS, OB, JZ), pp. 683–684.
DATE-2012-StattelmannGCBR #hybrid #modelling #simulation #using
Hybrid source-level simulation of data caches using abstract cache models (SS, GG, CC, OB, WR), pp. 376–381.
DATE-2012-ZimmermannBR #analysis #multi #power management
Analysis of multi-domain scenarios for optimized dynamic power management strategies (JZ, OB, WR), pp. 862–865.
DAC-2011-StattelmannBR #optimisation #performance #simulation
Fast and accurate source-level simulation of software timing considering complex code optimizations (SS, OB, WR), pp. 486–491.
DATE-2011-CroneBCDER #state of the art #verification
State of the art verification methodologies in 2015 (AC, OB, CC, BD, VE, MR), p. 1339.
DATE-2011-StattelmannBR #analysis #manycore #performance #simulation
Fast and accurate resource conflict simulation for performance analysis of multi-core systems (SS, OB, WR), pp. 210–215.
DATE-2010-BraunBLR #interface #specification #verification
Simulation-based verification of the MOST NetInterface specification revision 3.0 (AB, OB, DL, WR), pp. 538–543.
DATE-2010-MullerBGRNZB #design #implementation #manycore #recognition
Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation (MM, AGB, JG, WR, DN, JMZ, OB), pp. 532–537.
DATE-2009-ViehlPBR #analysis #performance #scheduling
White box performance analysis considering static non-preemptive software scheduling (AV, MP, OB, WR), pp. 513–518.
DAC-2008-SchnerrBVR #embedded #simulation
High-performance timing simulation of embedded software (JS, OB, AV, WR), pp. 290–295.
DATE-2007-KrauseBHTR #component #simulation
Timing simulation of interconnected AUTOSAR software-components (MK, OB, AH, GT, WR), pp. 474–479.
DAC-2006-KlingaufGBPB #modelling #named #transaction
GreenBus: a generic interconnect fabric for transaction level modelling (WK, RG, OB, PP, MB), pp. 905–910.
DATE-2006-ViehlSBR #analysis #design #modelling #performance #simulation #uml
Formal performance analysis and simulation of UML/SysML models for ESL design (AV, TS, OB, WR), pp. 242–247.
DATE-2005-SchnerrBR #agile #prototype #simulation
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs (JS, OB, WR), pp. 792–797.
DATE-v1-2004-SiebenbornBR #analysis #communication #design
Communication Analysis for System-On-Chip Design (AS, OB, WR), pp. 648–655.
DATE-2000-BringmannRM #architecture #multi #synthesis
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation (OB, WR, CM), pp. 326–332.
DATE-1998-BringmannR #synthesis
Cross-Level Hierarchical High-Level Synthesis (OB, WR), pp. 451–456.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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