BibSLEIGH — Wolfgang

Travelled to:

1 × Portugal
1 × United Kingdom
11 × Germany
13 × France
7 × USA

Collaborated with:

O.Bringmann A.Viehl J.Gerlach J.Ruf T.Kropf ∅ J.Schnerr S.Stattelmann D.Lettnin A.Hergenhan G.Haug U.Kebschull C.Hansen M.Bogdan M.Pressler T.Schönwald S.Schmitt T.Kuhn C.Barna A.Reutter H.Martin H.Wunderlich D.W.Hoffmann P.K.Nalla J.Oetjens N.Bannow A.G.Braun C.Gerum J.Zimmermann K.Haug A.Siebenborn A.Vörg M.Radetzki C.Menn F.Nascimento K.Weiß T.Steckstor A.Kunzmann M.Harrant G.Pelz P.Heckeler S.Huster S.Burg H.Eichelberger J.Behrend M.Mittag A.Krinke G.Jerke A.Braun F.Ghenassia S.Swan V.Schönknecht S.Reitemeyer W.Müller J.M.Kühn D.Peterson H.Amano G.Gebhard C.Cullmann C.M.S.Torres J.Ahopelto M.W.M.Graef R.M.Popp M.Krause G.Tabanoglu A.Burger M.Dobler M.Rafaila H.Yagi J.Engblom J.Andrews K.A.Vissers M.Serughetti M.Bensch D.Brugger W.G.Spruth P.Baeuerle P.M.Peranandam R.J.Weiss T.Oppold M.Winterholer M.Edwards Y.Kashai J.Laufenberg T.Nirmaier S.Lämmermann A.Jesser L.Hedrich M.Müller D.Nienhüser J.M.Zöllner D.Sciuto G.Martin P.Flake J.Srouji T.Kirsten J.Borel G.Matheron A.A.Jerraya S.Resve M.Rogers I.Rugen-Herzig F.Theewen D.Gajski E.Villar V.Gerousis D.Barton J.Plantin S.E.Ericsson P.Cavalloro G.G.d.Jong R.A.Bergamaschi T.Grötker M.Kawarabayashi M.C.v.Lier A.Mayer M.Meredith M.Milligan T.N.Lal M.Schröder N.J.Hill H.Preißl T.Hinterberger J.Mellinger T.Hofmann N.Birbaumer B.Schölkopf M.Becker M.Chaari S.Chakraborty R.Drechsler W.Ecker K.Grüttner T.Kruse C.Kuznik H.M.Le M.Mauderer D.Müller-Gritschneder F.Poppen H.Post S.Reiter S.Roth U.Schlichtmann A.v.Schwerin B.Tabacaru

Talks about:

system (18) design (15) simul (13) softwar (12) verif (9) level (9) base (9) embed (7) automot (6) analysi (6)

Person: Wolfgang Rosenstiel

DBLP: Rosenstiel:Wolfgang

Facilitated 1 volumes:

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1986

Wrote 59 papers:

DATE-2015-DoblerHRPRB #adaptation #identification #named: Bordersearch: an adaptive identification of failure regions (MD, MH, MR, GP, WR, MB), pp. 1036–1041.
DATE-2015-GerumBR #gpu #performance #simulation: Source level performance simulation of GPU cores (CG, OB, WR), pp. 217–222.
DATE-2015-KuhnPABR: Spatial and temporal granularity limits of body biasing in UTBB-FDSOI (JMK, DP, HA, OB, WR), pp. 876–879.
SEFM-2015-HusterBELRKR #performance #testing: Efficient Testing of Different Loop Paths (SH, SB, HE, JL, JR, TK, WR), pp. 117–131.
CBSE-2014-PresslerVBR #component #deployment #embedded #estimation #execution: Execution cost estimation for software deployment in component-based embedded systems (MP, AV, OB, WR), pp. 123–128.
DAC-2014-OetjensBBBBCCDEGKKLM0MPPRRRSSTV #challenge #evaluation #prototype #research #safety #state of the art #using: Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges (JHO, NB, MB, OB, AB, MC, SC, RD, WE, KG, TK, CK, HML, MM, WM, DMG, FP, HP, SR, WR, SR, US, AvS, BAT, AV), p. 6.
DATE-2014-NirmaierBHVBRP #assessment #robust: Mission profile aware robustness assessment of automotive power devices (TN, AB, MH, AV, OB, WR, GP), pp. 1–6.
SEFM-2014-HusterHERBKR #flexibility #invariant #specification: More Flexible Object Invariants with Less Specification Overhead (SH, PH, HE, JR, SB, TK, WR), pp. 302–316.
DATE-2013-SchonwaldVBR #deployment #memory management: Shared memory aware MPSoC software deployment (TS, AV, OB, WR), pp. 1771–1776.
DATE-2012-MittagKJR #constraints #design #geometry #physics: Hierarchical propagation of geometric constraints for full-custom physical design of ICs (MM, AK, GJ, WR), pp. 1471–1474.
DATE-2012-StattelmannGCBR #hybrid #modelling #simulation #using: Hybrid source-level simulation of data caches using abstract cache models (SS, GG, CC, OB, WR), pp. 376–381.
DATE-2012-TorresAGPR #benchmark #metric: Beyond CMOS — benchmarking for future technologies (CMST, JA, MWMG, RMP, WR), pp. 129–134.
DATE-2012-ZimmermannBR #analysis #multi #power management: Analysis of multi-domain scenarios for optimized dynamic power management strategies (JZ, OB, WR), pp. 862–865.
DAC-2011-StattelmannBR #optimisation #performance #simulation: Fast and accurate source-level simulation of software timing considering complex code optimizations (SS, OB, WR), pp. 486–491.
DATE-2011-BehrendLHRKR #embedded #hybrid #scalability #verification: Scalable hybrid verification for embedded software (JB, DL, PH, JR, TK, WR), pp. 179–184.
DATE-2011-StattelmannBR #analysis #manycore #performance #simulation: Fast and accurate resource conflict simulation for performance analysis of multi-core systems (SS, OB, WR), pp. 210–215.
DATE-2010-BraunBLR #interface #specification #verification: Simulation-based verification of the MOST NetInterface specification revision 3.0 (AB, OB, DL, WR), pp. 538–543.
DATE-2010-LammermannRKRVJH #design #towards #verification: Towards assertion-based verification of heterogeneous system designs (SL, JR, TK, WR, AV, AJ, LH), pp. 1171–1176.
DATE-2010-MullerBGRNZB #design #implementation #manycore #recognition: Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation (MM, AGB, JG, WR, DN, JMZ, OB), pp. 532–537.
DAC-2009-YagiREAVS #design: The wild west: conquest of complex hardware-dependent software design (HY, WR, JE, JA, KAV, MS), pp. 878–879.
DATE-2009-LettninNBRGKRSR #hardware #verification: Semiformal verification of temporal properties in automotive hardware dependent software (DL, PKN, JB, JR, JG, TK, WR, VS, SR), pp. 1214–1217.
DATE-2009-ViehlPBR #analysis #performance #scheduling: White box performance analysis considering static non-preemptive software scheduling (AV, MP, OB, WR), pp. 513–518.
DAC-2008-SchnerrBVR #embedded #simulation: High-performance timing simulation of embedded software (JS, OB, AV, WR), pp. 290–295.
DATE-2008-LettninNRKRKSR #embedded #verification: Verification of Temporal Properties in Automotive Embedded Software (DL, PKN, JR, TK, WR, TK, VS, SR), pp. 164–169.
DATE-2007-KrauseBHTR #component #simulation: Timing simulation of interconnected AUTOSAR software-components (MK, OB, AH, GT, WR), pp. 474–479.
ICEIS-AIDSS-2007-BenschBRBSB #operating system #optimisation #predict #self: Self-Learning Prediction System for Optimisation of Workload Management in a Mainframe Operating System (MB, DB, WR, MB, WGS, PB), pp. 212–218.
DAC-2006-PeranandamNRWKR #bound #performance: Fast falsification based on symbolic bounded property checking (PMP, PKN, JR, RJW, TK, WR), pp. 1077–1082.
DATE-2006-ViehlSBR #analysis #design #modelling #performance #simulation #uml: Formal performance analysis and simulation of UML/SysML models for ESL design (AV, TS, OB, WR), pp. 242–247.
DATE-DF-2006-BannowHR #automation #clustering #design #evaluation #performance: Automatic systemC design configuration for a faster evaluation of different partitioning alternatives (NB, KH, WR), pp. 217–218.
DATE-DF-2006-OetjensGR #design #flexibility #rule-based #specification: Flexible specification and application of rule-based transformations in an automotive design flow (JHO, JG, WR), pp. 82–87.
DATE-2005-RosenstielBGGKLMMMS #question #tool support: Is there a Market for SystemC Tools? (WR, RAB, FG, TG, MK, MCvL, AM, MM, MM, SS), p. 950.
DATE-2005-SchnerrBR #agile #prototype #simulation: Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs (JS, OB, WR), pp. 792–797.
ICML-2005-LalSHP #feedback #interface #online: A brain computer interface with online feedback based on magnetoencephalography (TNL, MS, NJH, HP, TH, JM, MB, WR, TH, NB, BS), pp. 465–472.
DATE-DF-2004-LettninBBGR #case study #design #embedded #network #synthesis: Synthesis of Embedded SystemC Design: A Case Study of Digital Neural Networks (DL, AGB, MB, JG, WR), pp. 248–255.
DATE-DF-2004-SchmittR #design #low cost #prototype #using #verification: Verification of a Microcontroller IP Core for System-on-a-Chip Designs Using Low-Cost Prototyping Environments (SS, WR), pp. 96–101.
DATE-v1-2004-SciutoMRSGFS #question: SystemC and SystemVerilog: Where do They Fit? Where are They Going? (DS, GM, WR, SS, FG, PF, JS), pp. 122–129.
DATE-v1-2004-SiebenbornBR #analysis #communication #design: Communication Analysis for System-On-Chip Design (AS, OB, WR), pp. 648–655.
DATE-v2-2004-VorgRR #cost analysis #metric: Measurement of IP Qualification Costs and Benefits (AV, MR, WR), pp. 996–1001.
DATE-2003-SchnerrHR #agile #prototype #set: Instruction Set Emulation for Rapid Prototyping of SoCs (JS, GH, WR), pp. 10562–10569.
DATE-2002-BorelMJRRRRT: MEDEA+ and ITRS Roadmaps (JB, GM, AAJ, SR, MR, WR, IRH, FT), p. 328.
DAC-2001-KuhnOWREK #framework #hardware #object-oriented #specification #synthesis #verification: A Framework for Object Oriented Hardware Specification, Verification, and Synthesis (TK, TO, MW, WR, ME, YK), pp. 413–418.
DATE-2001-GajskiVRGBPECJ #concurrent #specification: C/C++: progress or deadlock in system-level specification (DG, EV, WR, VG, DB, JP, SEE, PC, GGdJ), pp. 136–137.
DATE-2001-RufHGKRM #semantics #simulation: The simulation semantics of systemC (JR, DWH, JG, TK, WR, WM), pp. 64–70.
DATE-2001-RufHKR #multi: Simulation-guided property checking based on a multi-valued AR-automata (JR, DWH, TK, WR), pp. 742–748.
DATE-2000-BringmannRM #architecture #multi #synthesis: Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation (OB, WR, CM), pp. 326–332.
DATE-2000-HaugKR #design #framework #hardware #platform: A Hardware Platform for VLIW Based Emulation of Digital Designs (GH, UK, WR), p. 747.
DATE-2000-HergenhanR #analysis #architecture #embedded: Static Timing Analysis of Embedded Software on Advanced Processor Architectures (AH, WR), pp. 552–559.
DAC-1999-HansenNR #algorithm #approach #specification: An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications (CH, FN, WR), pp. 678–683.
DAC-1999-KuhnRK #hardware #java #simulation: Description and Simulation of Hardware/Software Systems with Java (TK, WR, UK), pp. 790–793.
DATE-1999-BarnaR #object-oriented #reuse: Object-Oriented Reuse Methodology for VHDL (CB, WR), p. 689–?.
DATE-1999-ReutterR #design #performance #reuse: An Efficient Reuse System for Digital Circuit Design (AR, WR), pp. 38–43.
DATE-1999-WeissSR #embedded #operating system #performance #realtime #using: Emulation of a Fast Reactive Embedded System using a Real Time Operating System (KW, TS, WR), pp. 764–765.
DATE-1998-BringmannR #synthesis: Cross-Level Hierarchical High-Level Synthesis (OB, WR), pp. 451–456.
DATE-1998-GerlachR #design #estimation #scalability: A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment (JG, WR), pp. 226–231.
DATE-1998-HansenKR #comparison #interface #simulation #synthesis #using #verification: Verification by Simulation Comparison using Interface Synthesis (CH, AK, WR), pp. 436–443.
DATE-1998-MartinR: A Comparing Study of Technology Mapping for FPGA (HGM, WR), pp. 939–940.
DATE-1998-Rosenstiel #design #industrial #standard #verification: Formal Verification: A New Standard CAD Tool for the Industrial Design Flow (WR), p. 422.
DATE-1998-Rosenstiel98a #design #generative #tool support: Next Generation System Level Design Tools (WR), p. 488–?.
DAC-1986-WunderlichR #fault #modelling #on the: On fault modeling for dynamic MOS circuits (HJW, WR), pp. 540–546.