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Travelled to:
2 × USA
Collaborated with:
S.Hur J.Lillis J.Cong G.Reinman M.Romesis
Talks about:
microarchitectur (1) algorithm (1) context (1) physic (1) insert (1) buffer (1) evalu (1) plan (1) fast (1) awar (1)

Person: Ashok Jagannathan

DBLP DBLP: Jagannathan:Ashok

Contributed to:

DAC 20032003
DAC 20002000

Wrote 2 papers:

DAC-2003-CongJRR #architecture #evaluation #physics
Microarchitecture evaluation with physical planning (JC, AJ, GR, MR), pp. 32–35.
DAC-2000-JagannathanHL #algorithm #performance
A fast algorithm for context-aware buffer insertion (AJ, SWH, JL), pp. 368–373.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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