Travelled to:1 × Germany
8 × USA
Collaborated with:J.Cong B.Grigorian M.Gill C.Liu M.A.Ghodrat N.Farahpour G.Memik W.H.Mangione-Smith A.Jagannathan M.Romesis Y.Hao B.Yuan K.Gururaj Y.Chen H.Huang B.Liu M.Potkonjak M.F.Chang A.Kaplan M.Naik E.Socher S.Tam
Talks about:architectur (3) network (3) acceler (3) rich (3) chip (3) cach (3) interconnect (2) microarchitectur (1) determinatio (1) reconfigur (1)
Person: Glenn Reinman
DBLP: Reinman:Glenn
Contributed to:
2015
201520142012
20122010200820032003Wrote 9 papers:
- DAC-2015-CongGHRY #architecture #network
- On-chip interconnection network for accelerator-rich architectures (JC, MG, YH, GR, BY), p. 6.
- HPCA-2015-GrigorianFR #approximate #named #reliability
- BRAINIAC: Bringing reliable accuracy into neurally-implemented approximate computing (BG, NF, GR), pp. 615–626.
- DAC-2014-CongGGGGR #architecture
- Accelerator-Rich Architectures: Opportunities and Progresses (JC, MAG, MG, BG, KG, GR), p. 6.
- DAC-2012-CongGGGR #architecture
- Architecture support for accelerator-rich CMPs (JC, MAG, MG, BG, GR), pp. 843–849.
- DATE-2012-ChenCHLLPR #configuration management #design #energy #hybrid
- Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design (YTC, JC, HH, BL, CL, MP, GR), pp. 45–50.
- DAC-2010-CongLR #concurrent #named
- ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip (JC, CL, GR), pp. 443–448.
- HPCA-2008-ChangCKNRST #multi
- CMP network-on-chip overlaid with multi-band RF-interconnect (MFC, JC, AK, MN, GR, ES, SWT), pp. 191–202.
- DAC-2003-CongJRR #architecture #evaluation #physics
- Microarchitecture evaluation with physical planning (JC, AJ, GR, MR), pp. 32–35.
- HPCA-2003-MemikRM
- Just Say No: Benefits of Early Cache Miss Determinatio (GM, GR, WHMS), pp. 307–316.