BibSLEIGH — Jason

Travelled to:

1 × China
1 × France
23 × USA
3 × Germany

Collaborated with:

C.Wu G.Reinman H.Huang P.Zhang B.Liu J.Xu Z.Zhang X.Yuan Y.Zou B.Xiao Y.Hwang S.Xu A.B.Kahng D.Chen Y.Fan M.Romesis C.Liu K.Gururaj M.Gill W.Jiang K.Minkovich T.Uchino D.Z.Pan P.H.Madden C.Chang Y.Ding M.Smith K.Khoo P.Li M.Huang M.A.Ghodrat B.Grigorian G.Luo Y.Shi J.Y.Lin S.K.Lim H.Li Z.Li R.Bagrodia K.Leung D.Zhou L.W.Hagen G.Robins B.Preas C.L.Liu K.The D.F.Wong A.Jagannathan R.Puri Y.Hao B.Yuan A.Papakonstantinou W.W.Hwu Y.Liang Y.Wang C.Zhang A.S.Sbîrlea Z.Budimlic V.Sarkar G.Han L.He D.Noice N.Shirali S.H.Yen Y.Chen M.Potkonjak M.F.Chang A.Kaplan M.Naik E.Socher S.Tam E.Haritan S.Krolikoski T.Kogel B.D.McCredie J.Shen A.Takach N.S.Nagaraj W.H.Joyner J.Burns M.Gavrielov R.Radojcic P.Rickert H.Stork N.Deo B.Zahiri I.Bolsens B.Gupta P.Lopresti C.B.Reynolds C.Rowen R.Simar

Talks about:

optim (13) base (10) map (10) level (9) interconnect (8) partit (8) fpga (8) synthesi (7) design (7) multi (7)

Person: Jason Cong

DBLP: Cong:Jason

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2006

2004

2003

2001

2000

1999

1998

1997

1996

1994

1993

1992

1991

1990

1989

Wrote 56 papers:

DAC-2015-CongGHRY #architecture #network: On-chip interconnection network for accelerator-rich architectures (JC, MG, YH, GR, BY), p. 6.
DAC-2015-ZhangHXHC #compilation #framework #named: CMOST: a system-level FPGA compilation framework (PZ, MH, BX, HH, JC), p. 6.
DAC-2014-CongGGGGR #architecture: Accelerator-Rich Architectures: Opportunities and Progresses (JC, MAG, MG, BG, KG, GR), p. 6.
DAC-2014-CongLXZ #architecture #clustering #reuse: An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers (JC, PL, BX, PZ), p. 6.
DAC-2013-CongX #fault #programmable: Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance (JC, BX), p. 8.
DAC-2013-PapakonstantinouCHCL #kernel #migration: Throughput-oriented kernel porting onto FPGAs (AP, DC, WmWH, JC, YL), p. 10.
DAC-2013-WangLZZC #array #clustering #memory management #multi #synthesis: Memory partitioning for multidimensional arrays in high-level synthesis (YW, PL, PZ, CZ, JC), p. 8.
DAC-2012-CongGGGR #architecture: Architecture support for accelerator-rich CMPs (JC, MAG, MG, BG, GR), pp. 843–849.
DAC-2012-CongL #architecture #metric #optimisation #synthesis: A metric for layout-friendly microarchitecture optimization in high-level synthesis (JC, BL), pp. 1239–1244.
DAC-2012-CongZZ #memory management #optimisation #synthesis: Optimizing memory hierarchy allocation with loop transformations for high-level synthesis (JC, PZ, YZ), pp. 1233–1238.
DATE-2012-ChenCHLLPR #configuration management #design #energy #hybrid: Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design (YTC, JC, HH, BL, CL, MP, GR), pp. 45–50.
DATE-2012-CongHLZZ #replication #source code #streaming: Combining module selection and replication for throughput-driven streaming programs (JC, MH, BL, PZ, YZ), pp. 1018–1023.
LCTES-2012-SbirleaZBCS #data flow #platform #programming: Mapping a data-flow programming model onto heterogeneous platforms (ASS, YZ, ZB, JC, VS), pp. 61–70.
DAC-2011-CongHLZ #memory management: A reuse-aware prefetching scheme for scratchpad memory (JC, HH, CL, YZ), pp. 960–965.
DAC-2011-CongLS #3d: Thermal-aware cell and through-silicon-via co-placement for 3D ICs (JC, GL, YS), pp. 670–675.
DAC-2010-CongLR #concurrent #named: ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip (JC, CL, GR), pp. 443–448.
DAC-2010-CongM #reliability: LUT-based FPGA technology mapping for reliability (JC, KM), pp. 517–522.
DATE-2010-CongHJ #algorithm #behaviour #pattern matching #pattern recognition #recognition #synthesis: A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis (JC, HH, WJ), pp. 1255–1260.
DATE-2010-CongLX #behaviour #coordination #optimisation #synthesis: Coordinated resource optimization in behavioral synthesis (JC, BL, JX), pp. 1267–1272.
DAC-2009-CongNPJBGRRS #question: Moore’s Law: another casualty of the financial meltdown? (JC, NSN, RP, WHJ, JB, MG, RR, PR, HS), pp. 202–203.
DAC-2009-PuriHKCKMST #challenge: From milliwatts to megawatts: system level power challenge (RP, EH, SK, JC, TK, BDM, JS, AT), pp. 750–751.
DATE-2009-CongG #energy #multi #performance #scheduling: Energy efficient multiprocessor task scheduling under input-dependent variation (JC, KG), pp. 411–416.
DATE-2008-CongX #network: Simultaneous FU and Register Binding Based on Network Flow Method (JC, JX), pp. 1057–1062.
HPCA-2008-ChangCKNRST #multi: CMP network-on-chip overlaid with multi-band RF-interconnect (MFC, JC, AK, MN, GR, ES, SWT), pp. 191–202.
DAC-2006-ChenCFX #multi: Optimality study of resource binding with multi-Vdds (DC, JC, YF, JX), pp. 580–585.
DAC-2006-CongFHJZ #behaviour #communication: Behavior and communication co-optimization for systems with sequential communication media (JC, YF, GH, WJ, ZZ), pp. 675–678.
DAC-2006-CongZ #algorithm #performance #scheduling: An efficient and versatile scheduling algorithm based on SDC formulation (JC, ZZ), pp. 433–438.
DAC-2006-LinCC #clustering #optimisation: Optimal simultaneous mapping and clustering for FPGA delay optimization (JYL, DC, JC), pp. 472–477.
DAC-2004-CongFZ #architecture #automation #pipes and filters #synthesis: Architecture-level synthesis for automatic interconnect pipelining (JC, YF, ZZ), pp. 602–607.
DAC-2004-DeoZBCGLRRS #question #what: What happened to ASIC?: Go (recon)figure? (ND, BZ, IB, JC, BG, PL, CBR, CR, RS), p. 185.
DAC-2003-CongJRR #architecture #evaluation #physics: Microarchitecture evaluation with physical planning (JC, AJ, GR, MR), pp. 32–35.
DAC-2003-CongY #multi: Multilevel global placement with retiming (JC, XY), pp. 208–213.
DAC-2001-CongR #clustering #multi: Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping (JC, MR), pp. 389–394.
DAC-2001-UchinoC #energy: An Interconnect Energy Model Considering Coupling Effects (TU, JC), pp. 555–558.
DAC-2000-CongH #array #incremental #programmable: Depth optimal incremental mapping for field programmable gate arrays (JC, HH), pp. 290–293.
DAC-2000-CongLW #clustering #multi #performance: Performance driven multi-level and multiway partitioning with retiming (JC, SKL, CW), pp. 274–279.
DAC-2000-CongY: Routing tree construction under fixed buffer locations (JC, XY), pp. 379–384.
DAC-1999-CongHX #performance: Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections (JC, YYH, SX), pp. 373–378.
DAC-1999-CongLW #clustering #optimisation #performance: Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization (JC, HL, CW), pp. 460–465.
DAC-1999-CongP #design #estimation: Interconnect Estimation and Dlanning for Deep Submicron Designs (JC, DZP), pp. 507–510.
DAC-1998-CongM #design #multi #performance: Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs (JC, PHM), pp. 356–361.
DAC-1998-CongW #performance: Optimal FPGA Mapping and Retiming with Efficient Initial State Computation (JC, CW), pp. 330–335.
DAC-1998-CongX: Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs (JC, SX), pp. 704–707.
DAC-1997-ChangC #approach #multi #performance: An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization (CCC, JC), pp. 600–603.
DAC-1997-CongHKNSY #2d #analysis: Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology (JC, LH, ABK, DN, NS, SHCY), pp. 627–632.
DAC-1997-CongW #pipes and filters #synthesis: FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits (JC, CW), pp. 644–649.
DAC-1996-CongH #composition #design: Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design (JC, YYH), pp. 726–729.
DAC-1994-CongLB #clustering #multi #network: Acyclic Multi-Way Partitioning of Boolean Networks (JC, ZL, RB), pp. 670–675.
DAC-1993-CongD #on the #trade-off: On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping (JC, YD), pp. 213–218.
DAC-1993-CongLZ #design #distributed: Performance-Driven Interconnect Design Based on Distributed RC Delay Model (JC, KSL, DZ), pp. 606–611.
DAC-1993-CongS #algorithm #bottom-up #clustering #design #parallel: A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design (JC, MS), pp. 755–760.
DAC-1993-KhooC #multi #performance: An Efficient Multilayer MCM Router Based on Four-Via Routing (KYK, JC), pp. 590–595.
DAC-1992-CongHK: Net Partitions Yield Better Module Partitions (JC, LWH, ABK), pp. 47–52.
DAC-1991-KahngCR #geometry #recursion: High-Performance Clock Routing Based on Recursive Geometric Aatching (ABK, JC, GR), pp. 322–327.
DAC-1990-CongPL #algorithm #design #modelling #standard: General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design (JC, BP, CLL), pp. 709–715.
DAC-1989-TheWC #layout: VIA Minimization by Layout Modification (KST, DFW, JC), pp. 799–802.