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Travelled to:
2 × USA
Collaborated with:
M.Marek-Sadowska
Talks about:
design (3) power (2) tree (2) interconnect (1) distribut (1) alphabet (1) topolog (1) buffer (1) optim (1) minim (1)

Person: Ashok Vittal

DBLP DBLP: Vittal:Ashok

Contributed to:

DAC 19951995
DAC 19941994

Wrote 3 papers:

DAC-1995-VittalM #design
Power Optimal Buffered Clock Tree Design (AV, MMS), pp. 497–502.
DAC-1995-VittalM95a #design
Power Distribution Topology Design (AV, MMS), pp. 503–507.
DAC-1994-VittalM #design #using
Minimal Delay Interconnect Design Using Alphabetic Trees (AV, MMS), pp. 392–396.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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