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Travelled to:
1 × France
Collaborated with:
H.Homayoun A.M.Eltawil F.J.Kurdahi
Talks about:
frequenc (1) process (1) aggress (1) voltag (1) variat (1) scale (1) sram (1) cach (1) awar (1)

Person: Avesta Sasan

DBLP DBLP: Sasan:Avesta

Contributed to:

DATE 20092009

Wrote 1 papers:

DATE-2009-SasanHEK #process #scalability
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling (AS, HH, AME, FJK), pp. 911–916.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.