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Travelled to:
1 × Germany
4 × USA
5 × France
Collaborated with:
A.C.Parker M.Xu N.Bagherzadeh C.Ramachandran D.S.Rao R.Maestre A.M.Eltawil M.Fernández R.Hermida M.J.Mlinar H.Singh A.Sasan H.Homayoun J.Liu P.H.Chou M.Sanchez-Elez A.Khajeh A.Gupta N.Dutt K.S.Khouri M.S.Abadir G.Lu E.M.C.Filho M.Lee
Talks about:
synthesi (4) reconfigur (3) schedul (3) awar (3) architectur (2) transfer (2) program (2) control (2) system (2) regist (2)

Person: Fadi J. Kurdahi

DBLP DBLP: Kurdahi:Fadi_J=

Contributed to:

DATE 20092009
DATE 20022002
DAC 20012001
DAC 20002000
DATE 19991999
DATE 19981998
ED&TC 19971997
DAC 19921992
DAC 19871987
DAC 19861986
DAC 19841984

Wrote 13 papers:

DATE-2009-KhajehGDKEKA #design #memory management #named #reliability
TRAM: A tool for Temperature and Reliability Aware Memory Design (AK, AG, ND, FJK, AME, KSK, MSA), pp. 340–345.
DATE-2009-SasanHEK #process #scalability
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling (AS, HH, AME, FJK), pp. 911–916.
DATE-2002-Sanchez-ElezFMMKHB #architecture #configuration management #multi
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures (MSE, MF, RM, RH, NB, FJK), pp. 547–552.
DAC-2001-LiuCBK #constraints #embedded #power management #scheduling
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems (JL, PHC, NB, FJK), pp. 840–845.
DAC-2000-SinghLFMLKB #case study #configuration management #multi #named
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications (HS, GL, EMCF, RM, MHL, FJK, NB), pp. 573–578.
DATE-1999-MaestreKBSHF #configuration management #kernel #scheduling
Kernel Scheduling in Reconfigurable Computing (RM, FJK, NB, HS, RH, MF), pp. 90–96.
DATE-1998-XuK #architecture #synthesis
Layout-Driven High Level Synthesis for FPGA Based Architectures (MX, FJK), pp. 446–450.
EDTC-1997-XuK #physics #synthesis
RTL synthesis with physical and controller information (MX, FJK), pp. 299–303.
EDAC-1994-RamachandranK #synthesis
Incorporating the Controller Effects During Register Transfer Level Synthesis (CR, FJK), pp. 308–313.
DAC-1992-RaoK #clustering
Partitioning by Regularity Extraction (DSR, FJK), pp. 235–238.
DAC-1987-KurdahiP #named
REAL: a program for REgister ALlocation (FJK, ACP), pp. 210–215.
DAC-1986-KurdahiP #estimation #named
PLEST: a program for area estimation of VLSI integrated circuits (FJK, ACP), pp. 467–473.
DAC-1984-ParkerKM #design #synthesis #verification
A general methodology for synthesis and verification of register-transfer designs (ACP, FJK, MJM), pp. 329–335.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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