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Travelled to:
1 × France
1 × USA
Collaborated with:
D.Chen Y.Chen S.Chilstedt
Talks about:
reconfigur (1) nanomateri (1) synthesi (1) circuit (1) aggress (1) insert (1) design (1) buffer (1) under (1) clock (1)

Person: Chen Dong

DBLP DBLP: Dong:Chen

Contributed to:

DAC 20102010
DATE 20092009

Wrote 2 papers:

DAC-2010-ChenDC #synthesis
Clock tree synthesis under aggressive buffer insertion (YYC, CD, DC), pp. 86–89.
DATE-2009-DongCC #configuration management #design
Reconfigurable circuit design with nanomaterials (CD, SC, DC), pp. 442–447.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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