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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × Germany
2 × USA
Collaborated with:
C.Yeh C.Wang L.Lee C.Yeh Y.Kang S.Shieh E.Hsu K.Cheng N.Chang S.Chou C.Chen C.Wen Y.Chan T.Chen
Talks about:
design (2) chip (2) interconnect (1) multimedia (1) techniqu (1) programm (1) variabl (1) support (1) voltag (1) suppli (1)

Person: Jinn-Shyan Wang

DBLP DBLP: Wang:Jinn=Shyan

Contributed to:

DAC 20092009
DATE Designers’ Forum 20062006
DAC 19991999

Wrote 4 papers:

DAC-2009-ChouCWCCWW #3d #manycore
No cache-coherence: a single-cycle ring interconnection for multi-core L1-NUCA sharing on 3D chips (SHC, CCC, CNW, YCC, TFC, CCW, JSW), pp. 587–592.
DATE-DF-2006-YehHCWC #design
An 830mW, 586kbps 1024-bit RSA chip design (CY, EFH, KWC, JSW, NJC), pp. 24–29.
DATE-DF-2006-YehWLW #multi #programmable
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications (CY, CCW, LCL, JSW), pp. 239–243.
DAC-1999-YehKSW #design #layout #using
Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs (CWY, YSK, SJS, JSW), pp. 62–67.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.