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Travelled to:
4 × USA
Collaborated with:
T.Kozawa H.Terai N.Kageyama T.Shimizu T.Ishii A.Tsukizoe J.Sakemi M.Hayase Y.Ogawa K.Kishida N.Yamada Y.Ohno
Talks about:
algorithm (4) placement (2) logic (2) vlsi (2) hierarch (1) approach (1) program (1) pattern (1) densiti (1) concurr (1)

Person: Chihei Miura

DBLP DBLP: Miura:Chihei

Contributed to:

DAC 19901990
DAC 19841984
DAC 19831983
DAC 19811981

Wrote 4 papers:

DAC-1990-KageyamaMS #algorithm #approach #linear #logic #optimisation #programming
Logic Optimization Algorithm by Linear Programming Approach (NK, CM, TS), pp. 345–348.
DAC-1984-KozawaMT #algorithm #layout #logic #top-down
Combine and top down block placement algorithm for hierarchical logic VLSI layout (TK, CM, HT), pp. 667–669.
DAC-1983-KozawaTIHMOKYO #algorithm #automation
Automatic placement algorithms for high packing density V L S I (TK, HT, TI, MH, CM, YO, KK, NY, YO), pp. 175–181.
DAC-1981-KozawaTSMI #algorithm #concurrent
A concurrent pattern operation algorithm for VLSI mask data (TK, AT, JS, CM, TI), pp. 563–570.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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