Travelled to:6 × USA
Collaborated with:T.Kozawa Y.Ogawa M.Hayase C.Miura Y.Ohno T.Ishii K.Gemma Y.Nagao Y.Satoh F.Goto K.Wakai M.Edagawa S.Hososaka M.Hashimoto Y.Shiraishi K.Yuyama K.Chiba K.Kishida N.Yamada
Talks about:high (4) placement (3) algorithm (3) procedur (2) concept (2) automat (2) layout (2) design (2) speed (2) basic (2)
Person: Hidekazu Terai
DBLP: Terai:Hidekazu
Contributed to:
1994199119881986198519841983Wrote 7 papers:
- DAC-1994-TeraiGNSO #automation #concept #design #performance
- Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1 (HT, KG, YN, YS, YO), pp. 262–269.
- DAC-1991-TeraiGWKEHH #automation #concept #design
- Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers (HT, FG, KW, TK, ME, SH, MH), pp. 193–198.
- DAC-1988-OgawaTK #automation #layout
- Automatic Layout Procedures for Serial Routing Devices (YO, HT, TK), pp. 642–645.
- DAC-1986-OgawaISTKYC #algorithm #optimisation #performance
- Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs (YO, TI, YS, HT, TK, KY, KC), pp. 404–410.
- DAC-1985-TeraiHK #array #metaprogramming #standard
- A routing procedure for mixed array of custom macros and standard cells (HT, MH, TK), pp. 503–508.
- DAC-1984-KozawaMT #algorithm #layout #logic #top-down
- Combine and top down block placement algorithm for hierarchical logic VLSI layout (TK, CM, HT), pp. 667–669.
- DAC-1983-KozawaTIHMOKYO #algorithm #automation
- Automatic placement algorithms for high packing density V L S I (TK, HT, TI, MH, CM, YO, KK, NY, YO), pp. 175–181.