Travelled to:1 × Germany
2 × USA
Collaborated with:J.Collard G.Hoflehner R.Ghiya D.C.Sehr A.Settle D.A.Connors S.Liao P.H.Wang H.Wang J.P.Shen
Talks about:itanium (2) optim (2) intel (2) architectur (1) processor (1) precomput (1) disambigu (1) softwar (1) program (1) prevent (1)
Person: Daniel M. Lavery
DBLP: Lavery:Daniel_M=
Contributed to:
2003
20022001Wrote 4 papers:
- CGO-2003-CollardL #optimisation
- Optimizations to Prevent Cache Penalties for the Intel ® Itanium 2 Processor (JFC, DML), pp. 105–114.
- CGO-2003-SettleCHL #architecture #optimisation #stack
- Optimization for the Intel® Itanium ®Architectur Register Stack (AS, DAC, GH, DML), pp. 115–124.
- PLDI-2002-LiaoWWSHL #adaptation
- Post-Pass Binary Adaptation for Software-Based Speculative Precomputation (SWL, PHW, HW, JPS, GH, DML), pp. 117–128.
- PLDI-2001-GhiyaLS #ambiguity #analysis #c #memory management #on the #points-to #source code
- On the Importance of Points-to Analysis and Other Memory Disambiguation Methods for C Programs (RG, DML, DCS), pp. 47–58.