BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Germany
1 × Mexico
1 × Spain
7 × USA
Collaborated with:
H.Wang P.H.Wang D.B.Noonburg A.S.Huang A.Wolfe M.B.Jr. R.Kling M.H.Lipasti C.B.Wilkerson J.D.Collins S.Liao R.N.Rakvic B.Black D.Limaye D.Kim T.M.Aamodt P.Chow P.Hammarlund K.Ramakrishnan E.Grochowski G.Hoflehner D.M.Lavery B.Greene K.Chan A.B.Yunus T.Sych S.F.Moore J.d.Cuvillo X.Tian X.Zou D.Yeung M.Girkar
Talks about:
processor (5) thread (3) architectur (2) experiment (2) precomput (2) prefetch (2) instruct (2) perform (2) itanium (2) specul (2)

Person: John Paul Shen

DBLP DBLP: Shen:John_Paul

Facilitated 1 volumes:


Contributed to:

ASPLOS 20042004
CGO 20042004
HPCA 20042004
HPCA 20022002
PLDI 20022002
HPCA 20012001
HPCA 19971997
ASPLOS 19961996
ASPLOS 19911991
DAC 19901990

Wrote 12 papers:

ASPLOS-2004-WangCWKGCYSMS #framework #multi #platform #thread
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform (PHW, JDC, HW, DK, BG, KMC, ABY, TS, SFM, JPS), pp. 144–155.
CGO-2004-KimLWCTZWYGS #physics #thread
Physical Experimentation with Prefetching Helper Threads on Intel’s Hyper-Threaded Processors (DK, SWL, PHW, JdC, XT, XZ, HW, DY, MG, JPS), pp. 27–38.
HPCA-2004-AamodtCHWS #hardware
Hardware Support for Prescient Instruction Prefetch (TMA, PC, PH, HW, JPS), pp. 84–95.
Non-Vital Loads (RNR, BB, DL, JPS), pp. 165–174.
HPCA-2002-WangWCGKS #execution #memory management
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation (PHW, HW, JDC, EG, RMK, JPS), pp. 187–196.
PLDI-2002-LiaoWWSHL #adaptation
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation (SWL, PHW, HW, JPS, GH, DML), pp. 117–128.
HPCA-2001-WangWKRS #execution #scheduling
Register Renaming and Scheduling for Dynamic Execution of Predicated Code (PHW, HW, RMK, KR, JPS), pp. 15–25.
HPCA-1997-NoonburgS #framework #modelling #performance #statistics
A Framework for Statistical Modeling of Superscalar Processor Performance (DBN, JPS), pp. 298–309.
ASPLOS-1996-HuangS #requirements #source code
The Intrinsic Bandwidth Requirements of Ordinary Programs (ASH, JPS), pp. 105–114.
ASPLOS-1996-LipastiWS #locality #predict
Value Locality and Load Value Prediction (MHL, CBW, JPS), pp. 138–147.
ASPLOS-1991-WolfeS #architecture
A Variable Instruction Stream Extension to the VLIW Architecture (AW, JPS), pp. 2–14.
DAC-1990-BreternitzS #architecture #synthesis
Architecture Synthesis of High-Performance Application-Specific Processors (MBJ, JPS), pp. 542–548.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.