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Travelled to:
1 × Germany
1 × Mexico
4 × USA
Collaborated with:
H.Wang J.P.Shen J.D.Collins R.Kling S.Liao X.Tian M.Girkar D.Kim K.Ramakrishnan E.Grochowski G.Hoflehner D.M.Lavery G.N.Chinya H.Jiang N.Y.Yang G.Lueh B.Greene K.Chan A.B.Yunus T.Sych S.F.Moore J.d.Cuvillo X.Zou D.Yeung
Talks about:
processor (3) thread (3) multithread (2) experiment (2) precomput (2) itanium (2) specul (2) helper (2) execut (2) base (2)

Person: Perry H. Wang

DBLP DBLP: Wang:Perry_H=

Contributed to:

PLDI 20072007
ASPLOS 20042004
CGO 20042004
HPCA 20022002
PLDI 20022002
HPCA 20012001

Wrote 6 papers:

PLDI-2007-WangCCJTGYLW #architecture #manycore #named #parallel #programming #thread
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system (PHW, JDC, GNC, HJ, XT, MG, NYY, GYL, HW), pp. 156–166.
ASPLOS-2004-WangCWKGCYSMS #framework #multi #platform #thread
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform (PHW, JDC, HW, DK, BG, KMC, ABY, TS, SFM, JPS), pp. 144–155.
CGO-2004-KimLWCTZWYGS #physics #thread
Physical Experimentation with Prefetching Helper Threads on Intel’s Hyper-Threaded Processors (DK, SWL, PHW, JdC, XT, XZ, HW, DY, MG, JPS), pp. 27–38.
HPCA-2002-WangWCGKS #execution #memory management
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation (PHW, HW, JDC, EG, RMK, JPS), pp. 187–196.
PLDI-2002-LiaoWWSHL #adaptation
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation (SWL, PHW, HW, JPS, GH, DML), pp. 117–128.
HPCA-2001-WangWKRS #execution #scheduling
Register Renaming and Scheduling for Dynamic Execution of Predicated Code (PHW, HW, RMK, KR, JPS), pp. 15–25.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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