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Travelled to:
1 × Canada
1 × Mexico
1 × Spain
2 × Germany
8 × USA
Collaborated with:
J.P.Shen P.H.Wang J.D.Collins A.Bracy R.Kling G.N.Chinya S.Liao S.Park S.Mitra S.Subramaniam G.H.Loh M.D.Linderman T.H.Y.Meng M.Yang B.Dong B.Zhang W.Hou M.Su H.Zhang X.Tian M.Girkar S.Zhang F.Lin C.Hsu K.Cheng D.Kim T.M.Aamodt P.Chow P.Hammarlund K.Ramakrishnan E.Grochowski G.Hoflehner D.M.Lavery Chit-Kwan Lin Andreas Wild T.Lin Mike Davies H.Jiang N.Y.Yang G.Lueh B.Greene K.Chan A.B.Yunus T.Sych S.F.Moore J.d.Cuvillo X.Zou D.Yeung
Talks about:
processor (4) thread (3) base (3) multithread (2) architectur (2) experiment (2) precomput (2) heterogen (2) prefetch (2) virtual (2)

Person: Hong Wang

DBLP DBLP: Wang:Hong

Contributed to:

DATE 20142014
DAC 20102010
HPCA 20092009
ASPLOS 20082008
PLDI 20072007
ASPLOS 20042004
CGO 20042004
HPCA 20042004
HPCA 20022002
ICPR v2 20022002
PLDI 20022002
CIKM 20012001
HPCA 20012001
PLDI 20182018

Wrote 14 papers:

DATE-2014-ZhangLHCW #multi #performance #predict
Joint Virtual Probe: Joint exploration of multiple test items’ spatial patterns for efficient silicon characterization and test prediction (SZ, FL, CKH, KTC, HW), pp. 1–6.
DAC-2010-ParkBWM #debugging #graph #locality #named #using
BLoG: post-silicon bug localization in processors using bug localization graphs (SBP, AB, HW, SM), pp. 368–373.
HPCA-2009-SubramaniamBWL #optimisation #performance
Criticality-based optimizations for efficient load processing (SS, AB, HW, GHL), pp. 419–430.
ASPLOS-2008-LindermanCWM #manycore #named #programming
Merge: a programming model for heterogeneous multi-core systems (MDL, JDC, HW, THYM), pp. 287–296.
PLDI-2007-WangCCJTGYLW #architecture #manycore #named #parallel #programming #thread
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system (PHW, JDC, GNC, HJ, XT, MG, NYY, GYL, HW), pp. 156–166.
ASPLOS-2004-WangCWKGCYSMS #framework #multi #platform #thread
Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform (PHW, JDC, HW, DK, BG, KMC, ABY, TS, SFM, JPS), pp. 144–155.
CGO-2004-KimLWCTZWYGS #physics #thread
Physical Experimentation with Prefetching Helper Threads on Intel’s Hyper-Threaded Processors (DK, SWL, PHW, JdC, XT, XZ, HW, DY, MG, JPS), pp. 27–38.
HPCA-2004-AamodtCHWS #hardware
Hardware Support for Prescient Instruction Prefetch (TMA, PC, PH, HW, JPS), pp. 84–95.
HPCA-2002-WangWCGKS #execution #memory management
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation (PHW, HW, JDC, EG, RMK, JPS), pp. 187–196.
ICPR-v2-2002-YangDWZ #estimation #mobile #realtime #using
Real-Time Pose Estimation for Outdoor Mobile Robots Using Range Data (MY, BD, HW, BZ), pp. 593–596.
PLDI-2002-LiaoWWSHL #adaptation
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation (SWL, PHW, HW, JPS, GH, DML), pp. 117–128.
CIKM-2001-HouSZW #database #mobile
An Optimal Construction of Invalidation Reports for Mobile Databases (WCH, MS, HZ, HW), pp. 458–465.
HPCA-2001-WangWKRS #execution #scheduling
Register Renaming and Scheduling for Dynamic Execution of Predicated Code (PHW, HW, RMK, KR, JPS), pp. 15–25.
PLDI-2018-LinWCLDW #architecture #manycore #network
Mapping spiking neural networks onto a manycore neuromorphic architecture (CKL, AW, GNC, THL, MD, HW), pp. 78–89.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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