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Travelled to:
3 × USA
Collaborated with:
S.Das P.N.Whatmough I.Darwazeh D.Blaauw K.Flautner R.Aitken G.S.Dasika K.Fan S.A.Mahlke
Talks about:
error (2) circuit (1) address (1) acceler (1) resili (1) margin (1) design (1) toler (1) shape (1) power (1)

Person: David M. Bull

DBLP DBLP: Bull:David_M=

Contributed to:

DAC 20112011
DAC 20092009
DAC 20082008

Wrote 3 papers:

DAC-2011-WhatmoughDBD #power management
Error-resilient low-power DSP via path-delay shaping (PNW, SD, DMB, ID), pp. 1008–1013.
DAC-2009-DasBBFA #design
Addressing design margins through error-tolerant circuits (SD, DB, DMB, KF, RA), pp. 11–12.
DAC-2008-DasikaDFMB #using
DVFS in loop accelerators using BLADES (GSD, SD, KF, SAM, DMB), pp. 894–897.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.