Travelled to:4 × USA
Collaborated with:D.M.Bull D.Blaauw P.N.Whatmough I.Darwazeh K.Flautner R.Aitken G.S.Dasika K.Fan S.A.Mahlke S.Lee V.Bertacco T.M.Austin T.N.Mudge
Talks about:circuit (2) error (2) architectur (1) address (1) acceler (1) resili (1) margin (1) design (1) toler (1) simul (1)
Person: Shidhartha Das
DBLP: Das:Shidhartha
Contributed to:
2011200920082004Wrote 4 papers:
- DAC-2011-WhatmoughDBD #power management
- Error-resilient low-power DSP via path-delay shaping (PNW, SD, DMB, ID), pp. 1008–1013.
- DAC-2009-DasBBFA #design
- Addressing design margins through error-tolerant circuits (SD, DB, DMB, KF, RA), pp. 11–12.
- DAC-2008-DasikaDFMB #using
- DVFS in loop accelerators using BLADES (GSD, SD, KF, SAM, DMB), pp. 894–897.
- DAC-2004-LeeDBABM #architecture #simulation
- Circuit-aware architectural simulation (SL, SD, VB, TMA, DB, TNM), pp. 305–310.