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Travelled to:
1 × France
3 × USA
Collaborated with:
J.Goodenough G.Yeric D.Flynn S.Das D.Blaauw D.M.Bull K.Flautner J.C.Rey N.S.Nagaraj A.B.Kahng F.Klass C.Hou L.Capodieci V.Singh
Talks about:
silicon (2) design (2) paperweight (1) parametr (1) practic (1) million (1) circuit (1) address (1) margin (1) improv (1)

Person: Rob Aitken

DBLP DBLP: Aitken:Rob

Contributed to:

DATE 20112011
DAC 20102010
DAC 20092009
DAC 20082008

Wrote 4 papers:

DATE-2011-AitkenYF #correlation #modelling #parametricity
Correlating models and silicon for improved parametric yield (RA, GY, DF), pp. 1159–1163.
DAC-2010-GoodenoughA #design
Post-silicon is too late avoiding the $50 million paperweight starts with validated designs (JG, RA), pp. 8–11.
DAC-2009-DasBBFA #design
Addressing design margins through error-tolerant circuits (SD, DB, DMB, KF, RA), pp. 11–12.
DAC-2008-ReyNKKAHCS #question
DFM in practice: hit or hype? (JCR, NSN, ABK, FK, RA, CH, LC, VS), pp. 898–899.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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