Travelled to:3 × USA
Collaborated with:Q.Liu C.Jung D.Lee S.Lee Y.Solihin J.Tuck S.Gupta J.H.Rogers D.Maxwell P.Rech S.S.Vazhkudai D.A.G.d.Oliveira D.Londo N.DeBardeleben P.O.A.Navaux L.Carro A.S.Bland
Talks about:system (2) error (2) multiprocessor (1) lightweight (1) understand (1) hardwar (1) acceler (1) thread (1) resili (1) implic (1)
Person: Devesh Tiwari
DBLP: Tiwari:Devesh
Contributed to:
2015
20152011Wrote 3 papers:
- HPCA-2015-TiwariGRMRVOLDN #comprehension #design #fault #gpu #scalability
- Understanding GPU errors on large-scale HPC systems and the implications for system design and operation (DT, SG, JHR, DM, PR, SSV, DAGdO, DL, ND, POAN, LC, ASB), pp. 331–342.
- LCTES-2015-LiuJLT #compilation #fault #lightweight #named
- Clover: Compiler Directed Lightweight Soft Error Resilience (QL, CJ, DL, DT), p. 10.
- HPCA-2011-LeeTST #fine-grained #multi #named #thread
- HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor (SL, DT, YS, JT), pp. 99–110.