BibSLEIGH — Luigi

Travelled to:

5 × USA
6 × Germany
8 × France

Collaborated with:

M.Negreiros A.A.Susin A.C.S.Beck É.F.Cota M.Lubaszewski A.A.d.S.Jr. M.B.Rutzig G.Gaydadjiev L.Sterpone F.R.Wagner M.S.Reorda E.L.Rhod C.A.L.Lisbôa F.Lima R.A.d.L.Reis S.A.Ito R.P.Jacobi L.B.d.Brisolara A.Vieira P.Faustini C.Lazzari P.F.Flores J.Monteiro F.L.Kastensmidt A.Orailoglu M.E.Kreutz M.Oyamada G.Nazarian D.G.Rodrigues Á.F.Moreira D.Matos S.Wong F.Fakhar G.P.Jahn D.T.Franco P.Rech N.DeBardeleben M.F.d.S.Oliveira R.M.Redin L.C.Lamb M.Renovell F.Azaïs Y.Bertrand L.A.Bautista-Gomez F.Cappello B.Fang S.Gurumurthi K.Pattabiraman K.Huang S.Han K.Popovici X.Guerin L.Li X.Yan S.Chae A.A.Jerraya D.Tiwari S.Gupta J.H.Rogers D.Maxwell S.S.Vazhkudai D.A.G.d.Oliveira D.Londo P.O.A.Navaux A.S.Bland

Talks about:

base (8) design (7) analog (6) low (6) system (5) reconfigur (4) test (4) cost (4) softwar (3) circuit (3)

Person: Luigi Carro

DBLP: Carro:Luigi

Contributed to:

2015

2014

2013

2011

2010

2008

2007

2006

2005

2004

2003

2002

2000

1999

1998

Wrote 26 papers:

DATE-2015-VieiraFCC #estimation #metric: NFRs early estimation through software metrics (AV, PF, LC, ÉFC), pp. 329–332.
HPCA-2015-TiwariGRMRVOLDN #comprehension #design #fault #gpu #scalability: Understanding GPU errors on large-scale HPC systems and the implications for system design and operation (DT, SG, JHR, DM, PR, SSV, DAGdO, DL, ND, POAN, LC, ASB), pp. 331–342.
PDP-2015-NazarianRMCG #control flow #detection #fault: Bit-Flip Aware Control-Flow Error Detection (GN, DGR, ÁFM, LC, GG), pp. 215–221.
DATE-2014-Bautista-GomezCCDFGPRR #how #named #reliability: GPGPUs: How to combine high computational power with high reliability (LABG, FC, LC, ND, BF, SG, KP, PR, MSR), pp. 1–9.
DATE-2013-RutzigBC #configuration management #energy #framework #multi #platform: A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation (MBR, ACSB, LC), pp. 1559–1564.
DATE-2011-SterponeCMWF #configuration management #power management: A new reconfigurable clock-gating technique for low power SRAM-based FPGAs (LS, LC, DM, SW, FF), pp. 752–757.
DATE-2010-LazzariFMC #multi: A new quaternary FPGA based on a voltage-mode multi-valued circuit (CL, PFF, JM, LC), pp. 1797–1802.
DATE-2008-BeckRGC #configuration management #embedded: Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications (ACSB, MBR, GG, LC), pp. 1208–1213.
DATE-2008-BrisolaraORLCW #code generation #uml #using: Using UML as Front-end for Heterogeneous Software Code Generation Strategies (LBdB, MFdSO, RMR, LCL, LC, FRW), pp. 504–509.
DAC-2007-HuangHPBGLyCCJ #case study #design: Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264 (KH, SIH, KP, LBdB, XG, LL, XY, SIC, LC, AAJ), pp. 39–42.
DATE-2007-RhodLC #architecture #performance: A low-SER efficient core processor architecture for future technologies (ELR, CALL, LC), pp. 1448–1453.
DATE-2006-NegreirosCS #reduction: An improved RF loopback for test time reduction (MN, LC, AAS), pp. 646–651.
DAC-2005-BeckC #configuration management: Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility (ACSB, LC), pp. 732–737.
DATE-2005-KastensmidtSCR #composition #design #logic #on the: On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs (FLK, LS, LC, MSR), pp. 1290–1295.
DATE-2005-NegreirosCS #evaluation #low cost #using: Noise Figure Evaluation Using Low Cost BIST (MN, LC, AAS), pp. 158–163.
DATE-DF-2004-JuniorC #design #low cost #statistics: Highly Digital, Low-Cost Design of Statistic Signal Acquisition in SoCs (AAdSJ, LC), pp. 10–15.
DATE-v1-2004-NegreirosCS #low cost #testing: Low Cost Analog Testing of RF Signal Paths (MN, LC, AAS), pp. 292–297.
DAC-2003-LimaCR #design #fault tolerance: Designing fault tolerant systems into SRAM-based FPGAs (FL, LC, RAdLR), pp. 650–655.
DAC-2003-NegreirosCS #low cost: Ultimate low cost analog BIST (MN, LC, AAS), pp. 570–573.
DATE-2002-CotaCLO #design #testing: Test Planning and Design Space Exploration in a Core-Based Environment (ÉFC, LC, ML, AO), pp. 478–485.
DATE-2000-CarroKWO #embedded #multi #synthesis: System Synthesis for Multiprocessor Embedded Applications (LC, MEK, FRW, MO), pp. 697–702.
DATE-2000-CarroSNJF #component: Non-Linear Components for Mixed Circuits Analog Front-End (LC, AAdSJ, MN, GPJ, DTF), pp. 544–549.
DATE-2000-CotaRABCL #reuse: Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte (ÉFC, MR, FA, YB, LC, ML), pp. 226–230.
DATE-2000-ItoCJ #design #java: System Design Based on Single Language and Single-Chip Java ASIP Microcontroller (SAI, LC, RPJ), pp. 703–707.
DATE-1999-CotaCL #adaptation #fault #linear #using: A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester (ÉFC, LC, ML), pp. 184–188.
DAC-1998-CarroN #adaptation #algorithm #performance: Efficient Analog Test Methodology Based on Adaptive Algorithms (LC, MN), pp. 32–37.