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Travelled to:
1 × USA
2 × France
Collaborated with:
R.Schwencker H.E.Graeb M.Pronath K.Antreich S.Zizala
Talks about:
circuit (2) design (2) analog (2) mismatch (1) boundari (1) paramet (1) general (1) feasibl (1) automat (1) analysi (1)

Person: Frank Schenkel

DBLP DBLP: Schenkel:Frank

Contributed to:

DATE 20022002
DAC 20012001
DATE 20002000

Wrote 3 papers:

DATE-2002-SchwenckerSPG #adaptation #parametricity #set #using #worst-case
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets (RS, FS, MP, HEG), pp. 581–585.
DAC-2001-SchenkelPZSGA #analysis #optimisation
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search (FS, MP, SZ, RS, HEG, KA), pp. 858–863.
DATE-2000-SchwenckerSGA #automation #bound #design
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits (RS, FS, HEG, KA), pp. 42–47.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.