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Travelled to:
2 × Germany
5 × France
6 × USA
Collaborated with:
K.Antreich U.Schlichtmann R.Schwencker D.Mueller M.Pronath F.Schenkel G.Stehr J.Eckmueller M.Zwerger V.Kleeberger T.Massier M.Groepl W.M.Lindermeir T.J.Vogels C.U.Wieser D.Binkley G.G.E.Gielen J.S.Roychowdhury J.Zou S.Zizala
Talks about:
analog (11) circuit (8) design (7) method (4) perform (3) analysi (3) optim (3) size (3) hierarch (2) boundari (2)

Person: Helmut E. Graeb

DBLP DBLP: Graeb:Helmut_E=

Contributed to:

DATE 20152015
DAC 20132013
DATE 20082008
DATE 20072007
DAC 20062006
DAC 20052005
DAC 20032003
DATE 20022002
DAC 20012001
DATE 20002000
DATE 19991999
DATE 19981998
DAC 19931993

Wrote 16 papers:

DATE-2015-ZwergerG #detection #symmetry
Detection of asymmetric aging-critical voltage conditions in analog power-down mode (MZ, HEG), pp. 1269–1272.
DAC-2013-KleebergerGS #evaluation #modelling #performance #predict #standard
Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies (VK, HEG, US), p. 6.
DATE-2008-BinkleyGGR #design
From Transistor to PLL — Analogue Design and EDA Methods (DB, HEG, GGEG, JSR).
DATE-2008-MassierGS #design
Sizing Rules for Bipolar Analog Circuit Design (TM, HEG, US), pp. 140–145.
DATE-2007-MuellerGS #design #polynomial #programming #trade-off #using
Trade-off design of analog circuits using goal attainment and “Wave Front” sequential quadratic programming (DM, HEG, US), pp. 75–80.
DAC-2006-ZouMGS #optimisation
A CPPLL hierarchical optimization methodology considering jitter, power and locking time (JZ, DM, HEG, US), pp. 19–24.
DAC-2005-MuellerSGS #performance
Deterministic approaches to analog performance space exploration (PSE) (DM, GS, HEG, US), pp. 869–874.
DAC-2003-StehrGA #analysis #bound #performance #trade-off
Performance trade-off analysis of analog circuits by normal-boundary intersection (GS, HEG, KA), pp. 958–963.
DATE-2002-PronathGA #design #fault #float
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits (MP, HEG, KA), pp. 78–83.
DATE-2002-SchwenckerSPG #adaptation #parametricity #set #using #worst-case
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets (RS, FS, MP, HEG), pp. 581–585.
DAC-2001-SchenkelPZSGA #analysis #optimisation
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search (FS, MP, SZ, RS, HEG, KA), pp. 858–863.
DATE-2000-SchwenckerSGA #automation #bound #design
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits (RS, FS, HEG, KA), pp. 42–47.
DATE-1999-SchwenckerEGA #automation #constraints
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints (RS, JE, HEG, KA), pp. 323–327.
Hierarchical Characterization of Analog Integrated CMOS Circuits (JE, MG, HEG), pp. 636–643.
DATE-1998-LindermeirVG #design #detection #fault #metric #parametricity
Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults (WML, TJV, HEG), pp. 822–827.
DAC-1993-GraebWA #analysis #optimisation #worst-case
Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances (HEG, CUW, KA), pp. 142–147.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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