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Travelled to:
1 × Germany
1 × USA
2 × France
Collaborated with:
H.E.Graeb K.Antreich R.Schwencker F.Schenkel U.Schlichtmann S.Zizala M.Schmidt H.Kinzelbach V.Glöckel M.Dietrich U.Eichler J.Haase M.Bühler J.Koehl J.Bickford J.Hibbeler R.Sommer A.Ripp
Talks about:
design (5) circuit (3) analog (3) yield (2) digit (2) methodolog (1) manufactur (1) crossroad (1) mismatch (1) influenc (1)

Person: Michael Pronath

DBLP DBLP: Pronath:Michael

Contributed to:

DATE 20092009
DATE 20062006
DATE 20022002
DAC 20012001

Wrote 5 papers:

DATE-2009-SchlichtmannSKPGDEH #design #how #statistics
Digital design at a crossroads How to make statistical design methodologies industrially relevant (US, MS, HK, MP, VG, MD, UE, JH), pp. 1542–1547.
DATE-2006-BuhlerKBHSSPR #design #process
DFM/DFY design for manufacturability and yield — influence of process variations in digital, analog and mixed-signal circuit design (MB, JK, JB, JH, US, RS, MP, AR), pp. 387–392.
DATE-2002-PronathGA #design #fault #float
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits (MP, HEG, KA), pp. 78–83.
DATE-2002-SchwenckerSPG #adaptation #parametricity #set #using #worst-case
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets (RS, FS, MP, HEG), pp. 581–585.
DAC-2001-SchenkelPZSGA #analysis #optimisation
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search (FS, MP, SZ, RS, HEG, KA), pp. 858–863.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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