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Travelled to:
1 × USA
2 × France
2 × Germany
Collaborated with:
H.E.Graeb F.Schenkel K.Antreich M.Pronath J.Eckmueller W.Ecker V.Esen T.Steininger M.Velten S.Zizala
Talks about:
circuit (3) analog (3) design (2) size (2) constraint (1) structur (1) mismatch (1) consider (1) boundari (1) paramet (1)

Person: Robert Schwencker

DBLP DBLP: Schwencker:Robert

Contributed to:

DATE 20102010
DATE 20022002
DAC 20012001
DATE 20002000
DATE 19991999

Wrote 5 papers:

DATE-2010-EckerESSV #embedded #modelling
TLM+ modeling of embedded HW/SW systems (WE, VE, RS, TS, MV), pp. 75–80.
DATE-2002-SchwenckerSPG #adaptation #parametricity #set #using #worst-case
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets (RS, FS, MP, HEG), pp. 581–585.
DAC-2001-SchenkelPZSGA #analysis #optimisation
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search (FS, MP, SZ, RS, HEG, KA), pp. 858–863.
DATE-2000-SchwenckerSGA #automation #bound #design
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits (RS, FS, HEG, KA), pp. 42–47.
DATE-1999-SchwenckerEGA #automation #constraints
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints (RS, JE, HEG, KA), pp. 323–327.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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