Person: Kurt Antreich

DBLP: Antreich:Kurt

Contributed to:

2003

2002

2002

2001

2000

1999

1995

1994

1993

Wrote 10 papers:

DAC-2003-StehrGA #analysis #bound #performance #trade-off

Performance trade-off analysis of analog circuits by normal-boundary intersection (GS, HEG, KA), pp. 958–963.

DAC-2002-KolblKAD #simulation

Handling special constructs in symbolic simulation (AK, JHK, KA, RFD), pp. 105–110.

DATE-2002-PronathGA #design #fault #float

A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits (MP, HEG, KA), pp. 78–83.

DAC-2001-SchenkelPZSGA #analysis #optimisation

Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search (FS, MP, SZ, RS, HEG, KA), pp. 858–863.

DATE-2000-SchwenckerSGA #automation #bound #design

The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits (RS, FS, HEG, KA), pp. 42–47.

DATE-1999-SchwenckerEGA #automation #constraints

Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints (RS, JE, HEG, KA), pp. 323–327.

DAC-1995-RohfleischWA #analysis #logic #optimisation

Logic Clause Analysis for Delay Optimization (BR, BW, KA), pp. 668–672.

DAC-1995-WurthEA #algorithm #composition #functional #multi

Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm (BW, KE, KA), pp. 54–59.

DAC-1994-HenftlingWA #fault #simulation

Path Hashing to Accelerate Delay Fault Simulation (MH, HCW, KA), pp. 522–526.

DAC-1993-GraebWA #analysis #optimisation #worst-case

Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances (HEG, CUW, KA), pp. 142–147.