Travelled to:1 × France
2 × USA
2 × United Kingdom
Collaborated with:S.Kumar P.Ancilotti M.D.Natale L.Carnevali A.Pinzuti E.Vicario P.Gai M.Trimarchi G.Guidi S.Mazzini M.D'Alessandro A.Domenici T.Vardanega L.Palopoli L.Abeni F.Conticelli P.Pagano M.Chitnis A.Romano R.Severino M.Alves P.G.Sousa E.Tovar
Talks about:system (3) hierarch (2) network (2) time (2) real (2) base (2) uml (2) hrt (2) processor (1) implement (1)
Person: Giuseppe Lipari
DBLP: Lipari:Giuseppe
Contributed to:
2014
2011
2009
20042003
2001Wrote 6 papers:
- PDP-2014-KumarL #analysis #latency #manycore
- Latency Analysis of Network-on-Chip Based Many-Core Processors (SK, GL), pp. 432–439.
- AdaEurope-2011-CarnevaliLPV #approach #design #formal method #scheduling #verification
- A Formal Approach to Design and Verification of Two-Level Hierarchical Scheduling Systems (LC, GL, AP, EV), pp. 118–131.
- SAC-2009-PaganoCRLSAST #implementation #network #realtime
- ERIKA and open-ZB: an implementation for real-time wireless networking (PP, MC, AR, GL, RS, MA, PGS, ET), pp. 1687–1688.
- CBSE-2004-LipariGTGA #component #framework #realtime
- A Hierarchical Framework for Component-Based Real-Time Systems (GL, PG, MT, GG, PA), pp. 209–216.
- AdaEurope-2003-MazziniDNDLV #named #uml
- HRT-UML: Taking HRT-HOOD onto UML (SM, MD, MDN, AD, GL, TV), pp. 405–416.
- LCTES-OM-2001-PalopoliLANAC #embedded #performance #prototype #simulation
- A Tool for Simulation and Fast Prototyping of Embedded Control Systems (LP, GL, LA, MDN, PA, FC), pp. 73–81.