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Travelled to:
2 × USA
Collaborated with:
K.Tamaru M.Hashimoto Y.Taniguchi
Talks about:
placement (1) techniqu (1) practic (1) reduct (1) layout (1) glitch (1) design (1) consid (1) branch (1) resiz (1)

Person: Hidetoshi Onodera

DBLP DBLP: Onodera:Hidetoshi

Contributed to:

DAC 19991999
DAC 19911991

Wrote 2 papers:

DAC-1999-HashimotoOT #design #power management #reduction
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design (MH, HO, KT), pp. 446–451.
DAC-1991-OnoderaTT #bound #layout
Branch-and-Bound Placement for Building Block Layout (HO, YT, KT), pp. 433–439.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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